JPH0851113A - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To widely use the automatic centering function of a wire bonding device for a semiconductor integrated circuit having various pad forms. CONSTITUTION:A semiconductor integrated circuit has a circuit forming surface 2 on one side surface and a wire bonding electrode pad 4 formed on the surface 2 in such a manner that the wire bonding region 5 of the pad 4 is exposed and the other pad region is covered with a reflection preventive film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of electrode pads for wire bonding on the side where a circuit is formed and a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, in wire bonding technology, an electrode pad pitch reduction technology in a semiconductor integrated circuit is an important theme. This is because with the development of Al (aluminum) thinning technology, the area of the semiconductor function part becomes smaller,
This is because the factor that determines the chip size is the pad pitch. As the chip size becomes smaller, the yield per wafer increases correspondingly, resulting in cost reduction. Therefore, in order to reduce the pad pitch, it is essential to improve the positional accuracy of wire bonding.

Generally, when performing wire bonding, it is necessary to make the wire bonding device remember the connection position between the electrode pad of the semiconductor chip and the inner lead of the lead frame. This is called teaching,
In this teaching, the operator makes an alignment with the center of the electrode pad while looking at the monitor screen of the wire bonding apparatus. Therefore, as a matter of course, visual error between operators and individual differences between operators occur during teaching, and as a result, adjacent bonding wires and bonding tools come into contact during wire bonding, causing wire bending and wire shorts. However, there is a limit to reducing the pad pitch.

Therefore, at present, a wire bonding apparatus having an automatic centering function for electrode pads has been developed. This is because the shape and size of the electrode pad are memorized in the wire bonding device in advance, the image of the actual electrode pad captured by the optical camera is binarized, and the image of the electrode pad that is whitishly raised and the The automatic centering is performed by comparing with the pad image that has been memorized.

[0005]

However, in the conventional semiconductor integrated circuit, when the image of the electrode pad captured by the optical camera is binarized, it is extracted from the electrode pad 30 as shown in FIG. 4 (a). Wiring part 31
Also floats up whitish together with the electrode pad 30, so that the pad image memorized in the wire bonding apparatus and the pad image actually recognized by the apparatus cannot be matched, and the automatic centering function cannot be used.

Further, as shown in FIG. 4B, even when the interval (pad pitch) between adjacent electrode pads 30 becomes extremely narrow, the boundary between the pads cannot be detected due to the reflection on the pad surface. The wire bonding apparatus mistakenly recognizes the plurality of electrode pads 30 as one electrode pad 30, and the automatic centering function cannot be used as described above. Furthermore, since only one pad image can be stored in the wire bonding device,
As shown in (c), the automatic centering function cannot be used even when the electrode pads 30 having different shapes or sizes are mixed in one semiconductor integrated circuit.

The present invention has been made to solve the above problems, and an object of the present invention is to widely use the automatic centering function of a wire bonding apparatus for semiconductor integrated circuits having various pad configurations. It is in.

[0008]

The present invention has been made in order to achieve the above-mentioned object, and one surface is used as a circuit forming surface, and a plurality of electrode pads for wire bonding are formed on the circuit forming surface. In the semiconductor integrated circuit, the plurality of electrode pads formed on the circuit formation surface have a structure in which the pad regions other than the respective wire bonding regions are covered with the antireflection film.

[0009]

The semiconductor integrated circuit of the present invention has an automatic centering function because the region other than the wire bonding region of the electrode pad region is covered with the antireflection film. By making the wire bonding device remember the pad shape corresponding to the wire bonding area in advance, the automatic centering function can be used for various types of electrode pads.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A and 1B are views for explaining an embodiment of a semiconductor integrated circuit according to the present invention, in which FIG. 1A is an enlarged view of a main part thereof, and FIG.

In FIG. 1, reference numeral 1 denotes a circuit base material which is a base of a semiconductor integrated circuit, and one surface 2 of the circuit base material 1 is provided.
An appropriate electronic circuit is formed by appropriately applying impurities and forming an insulating film, for example, by integrating components such as a transistor, a diode, a resistor, and a capacitor. A wiring pattern 3 made of, for example, aluminum is formed on the circuit forming surface 2 of the circuit substrate 1 together with various components manufactured by a film forming technique. Formed electrode pads (in this case, aluminum electrode pads) 4 are formed respectively.

These electrode pads 4 are portions to which bonding wires such as gold wires are connected at the time of wire bonding, and at the time of wire bonding, the individual electrode pads 4 are, for example, lead frames (inner leads, etc.) for external extraction. Is connected via a bonding wire. Incidentally, as the arrangement state of the electrode pads 4 on the circuit formation surface 2, most of them are formed in a fixed arrangement form on the peripheral portion outside the active region where the electronic circuit is constructed. Then, the one in which the electrode pad 4 is formed near the center of the circuit formation surface 2 is also proposed.

Here, the semiconductor integrated circuit of the present embodiment is different from the above-mentioned conventional example in the structure of the electrode pad 4 formed on the circuit forming surface 2 of the circuit substrate 1. That is, in this embodiment, as shown in FIG. 1, other pad regions (hatched portion in the drawing) of the electrode pads 4 except the wire bonding region 5 are formed together with the wiring pattern 3, for example, Ti.
It is covered with an antireflection film 6 using an ON film. By the way, the wire bonding region 5 of each electrode pad 4
Is an area that is appropriately set according to the thickness of the bonding wire to be connected and its ball crimping diameter,
In one semiconductor integrated circuit, all the electrode pads 4 are set as a common area (having the same shape and size).

Therefore, when wire bonding is performed by a wire bonding device having an automatic centering function, when the pad image captured by the optical camera is binarized, the antireflection film 6 in the area of the electrode pad 4 is formed. Only the image of the wire bonding area 5 which is not covered with is highlighted whitish. For this reason,
If the pad shape corresponding to the wire bonding area 5 of the electrode pad 4 is previously memorized in the wire bonding device, the memorized pad shape and the pad image obtained by the binarized image are always matched. Therefore, the wiring part 3 drawn out from the electrode pad 4 does not appear whitish together with the electrode pad 4 unlike the conventional case, and the automatic centering function cannot be used. It becomes possible to perform wire bonding.

Next, a method of manufacturing the semiconductor integrated circuit in this embodiment will be briefly described with reference to FIG. First, in the first step, as shown in FIG.
An oxide film (SiO ₂ ) 11 is formed on an Si (silicon) substrate 10 serving as a circuit substrate by an oxidizing device. Next, in the second step, as shown in FIG.
A conductive film 12 made of, for example, an aluminum film is formed on the oxide film 11 formed in step 1 by a sputtering device, and in the third step, as shown in FIG.
An antireflection film 13 is formed on the above. This antireflection film 13
When forming aluminum wiring by photo etching method,
In order to prevent favorable etching from being disturbed by diffused reflection of light, it is usually coated with a film thickness of 20 to 50 nm. In this embodiment, a TiON film is used as a film forming material having a low reflectance. .

Subsequently, in a fourth step, as shown in FIG. 3D, the conductive film 12 and the antireflection film 13 are removed by photoetching at predetermined portions to form a circuit substrate.
The antireflection film 1 is formed on one surface (the upper surface in FIG. 2) of the i substrate 10.
A plurality of (only one is shown in FIG. 2) electrode pads 14 and aluminum wirings 15 covered by 3 are formed. At this point, since the entire area of the electrode pad 14 is covered with the antireflection film 13, the bonding wire cannot be connected to the electrode pad 14 as it is.

Therefore, conventionally, the antireflection film 13 adhered to the electrode pad 14 and the aluminum wiring 15 is entirely removed to expose the entire region of the electrode pad 14, but in the present embodiment, as shown in FIG. As shown in FIG. 2E, the antireflection film 13 attached to the wire bonding region 16 of the electrode pad 14 is removed, and the other pad regions are left covered with the antireflection film 13. As a result, the same pad structure as that of the semiconductor integrated circuit shown in FIG. 1 can be manufactured.

The manufacturing method of this embodiment described above is as shown in FIG.
No change is made to the conventional manufacturing method except that the antireflection film 13 is removed only in a specific region (wire bonding region 16) in the final step shown in FIG. The semiconductor integrated circuit shown in can be obtained.

FIG. 3 is a diagram for explaining another embodiment of the semiconductor integrated circuit according to the present invention. First, FIG. 3A shows a case where the pad form on the circuit formation surface is applied to a semiconductor integrated circuit in which the interval between adjacent electrode pads 4 is extremely narrow. In this case as well, similar to FIG. The other pad regions (hatched portions in the drawing) of the electrode pads 4 except the wire bonding region 5 are covered with the antireflection film 6.

Conventionally, in such a pad form, since the pad pitch is extremely narrow, there is a problem that a plurality of (for example, two) electrode pads 4 are mistakenly recognized as one electrode pad 4 on the wire bonding apparatus side. , Fig. 3
If the pad structure shown in (a) is adopted, the antireflection film 6 is interposed at the boundary between the adjacent electrode pads 4, so that the center position of each electrode pad 4 can be reliably detected by the automatic centering function. become.

On the other hand, FIG. 3B shows a case where the present invention is applied to a semiconductor integrated circuit in which electrode pads 4 having different shapes or sizes are mixed as the electrode pad form on the circuit formation surface. Similarly to the above, other pad regions (hatched portions in the drawing) of the respective electrode pads 4 except the wire bonding region 5 are covered with the antireflection film 6.

Conventionally, in such a pad form, since the shape or size of the electrode pad 4 is different, it is not possible to compare the pad images memorized in the wire bonding apparatus with the binary images of all the electrode pads 4. However, if the pad structure shown in FIG. 3B is adopted, since the wire bonding regions 5 of the individual electrode pads 4 are common, the center position of each electrode pad 4 is automatically compared with the binarized image. The centering function enables reliable detection.

Further, FIG. 3 (c) and FIG. 3 (d)
FIG. 3 shows a case where the electrode pad form on the circuit formation surface is applied to a semiconductor integrated circuit in which a plurality of wire bonding regions 5 are set in one electrode pad 4.
In the case of (c), two wire bonding regions 5 are set in one electrode pad 4, and in the case of FIG. 3D, four wire bonding regions 5 are set in one electrode pad 4. Also in these cases, similarly to the above, other pad regions (hatched portions in the drawing) of the electrode pads 4 excluding the wire bonding regions 5 are covered with the antireflection film 6.

Conventionally, in such a pad form, although a plurality of wire bonding regions 5 are set in one electrode pad 4, only the center position P of each electrode pad 4 is detected by the automatic centering function of the wire bonding apparatus. Therefore, the automatic centering function could not be utilized for the actual wire bonding area 5. However, FIG. 3 (c) and FIG.
If the pad structure shown in (d) is adopted, even if a plurality of wire bonding regions 5 are set in one electrode pad 4, since each wire bonding region 5 is common, The center position of the wire bonding region 5 on each electrode pad 4 can be reliably detected by the automatic centering function in comparison with the binary image captured by the camera.

Although only the method of manufacturing the semiconductor integrated circuit shown in FIG. 1 has been described in the above embodiment, this can also be applied to the method of manufacturing semiconductor integrated circuits having various pad configurations shown in FIG. Needless to say.

[0026]

As described above, according to the present invention,
A wire bonding apparatus having an automatic centering function because the area other than the wire bonding area of each electrode pad area formed on the circuit formation surface is covered with the antireflection film. By memorizing the pad shape corresponding to the wire bonding area in advance, if the pad pitch is extremely narrow or if electrode pads of different shapes or sizes are mixed, it is also possible to use multiple wires in one electrode pad. When the bonding area is set, the automatic centering function can be widely used for semiconductor integrated circuits having various pad configurations.

As a result, it is possible to improve the accuracy of the teaching in wire bonding for semiconductor integrated circuits having various pad configurations, so that the pad pitch can be further reduced. Further, since the chip size can be reduced by this, the yield per wafer is improved and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 3 is a diagram for explaining another embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of symbols]

 1 Circuit Base Material 2 Circuit Forming Surface 3 Wiring Pattern 4 Electrode Pad 5 Wire Bonding Area 6 Antireflection Film

Claims (4)

[Claims] 1. A semiconductor integrated circuit in which one surface is a circuit forming surface and a plurality of electrode pads for wire bonding are formed on the circuit forming surface, wherein the plurality of electrode pads exclude respective wire bonding regions. A semiconductor integrated circuit, wherein the other pad region is covered with an antireflection film. 2. An electrode pad having a different shape or size is mixed on the circuit formation surface.
The semiconductor integrated circuit described. 3. The semiconductor integrated circuit according to claim 1, wherein a plurality of wire bonding regions are set in one electrode pad. 4. The method for manufacturing a semiconductor integrated circuit according to claim 1, 2 or 3, wherein first, a conductive film and an antireflection film are sequentially formed on one surface of a circuit substrate, and then, A predetermined portion of the conductive film and the antireflection film is removed to form a plurality of electrode pads covered with the antireflection film on one surface of the circuit substrate, and subsequently, in a wire bonding region of the electrode pad. A method for manufacturing a semiconductor integrated circuit, which comprises removing an adhered antireflection film.