JPS648733U - - Google Patents

Info

Publication number
JPS648733U
JPS648733U JP1987102521U JP10252187U JPS648733U JP S648733 U JPS648733 U JP S648733U JP 1987102521 U JP1987102521 U JP 1987102521U JP 10252187 U JP10252187 U JP 10252187U JP S648733 U JPS648733 U JP S648733U
Authority
JP
Japan
Prior art keywords
mark
diffusion layer
utility
model registration
automatic bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987102521U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987102521U priority Critical patent/JPS648733U/ja
Publication of JPS648733U publication Critical patent/JPS648733U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はいずれも本考案に関するもので、第１図は
本考案による半導体チツプの自動ボンデイング用
標識の実施例を示す半導体チツプ内標識部の拡大
平面図および断面図、第２図には本考案による標
識を利用したボンデイングの様子を例示する半導
体チツプの平面図である。図において、 １：半導体チツプの基板、２：酸化硅素膜、３
：拡散層、３ａ：標識を構成する拡散層表面、４
：標識を構成する金属膜、５：窒化硅素膜、６：
半導体チツプの組込回路、７：バンプ電極、８：
接続パツド、１０，１１：標識、２０，２１：半
導体チツプ、３１：フイルムキヤリア、３２：リ
ード線、３３：ボンデイング線、である。 The figures are all related to the present invention; Fig. 1 is an enlarged plan view and a sectional view of a marking part inside a semiconductor chip showing an embodiment of the marking for automatic bonding of a semiconductor chip according to the invention, and Fig. 2 is a cross-sectional view of a marking part in a semiconductor chip according to the invention. FIG. 2 is a plan view of a semiconductor chip illustrating bonding using a marker. In the figure, 1: semiconductor chip substrate, 2: silicon oxide film, 3
: Diffusion layer, 3a: Diffusion layer surface constituting the label, 4
: Metal film constituting the label, 5: Silicon nitride film, 6:
Embedded circuit of semiconductor chip, 7: Bump electrode, 8:
Connection pads, 10, 11: label, 20, 21: semiconductor chip, 31: film carrier, 32: lead wire, 33: bonding wire.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体チツプに対する自動ボンデイングに
よる接続の際にボンデイングを施すべき場所の割
り出し上の基準とするため半導体チツプの表面に
設けられる光センサにより検出可能な標識であつ
て、半導体チツプの基板の表面から作り込まれた
拡散層の入射光に対して実質的に露出された低反
射率の表面と、該拡散層表面の中央部分に被着さ
れた入射光に対して高反射率の金属膜とからなる
半導体チツプの自動ボンデイング用標識。 (2) 実用新案登録請求の範囲第１項に記載の標
識において、標識としての拡散層が燐を高い濃度
で拡散させたｎ形層であることを特徴とする半導
体チツプの自動ボンデイング用標識。 (3) 実用新案登録請求の範囲第１項に記載の標
識において、標識としての拡散層表面のまわりの
基板表面が酸化硅素膜により覆われたことを特徴
とする半導体チツプの自動ボンデイング用標識。 (4) 実用新案登録請求の範囲第１項に記載の標
識において、金属膜がアルミ膜であることを特徴
とする半導体チツプの自動ボンデイング用標識。 (5) 実用新案登録請求の範囲第１項に記載の標
識において、標識が窒化硅素膜により保護された
ことを特徴とする半導体チツプの自動ボンデイン
グ用標識。[Scope of Claim for Utility Model Registration] (1) A mark that can be detected by an optical sensor provided on the surface of a semiconductor chip for use as a reference for determining the location where bonding should be performed when connecting to a semiconductor chip by automatic bonding. The surface of the diffusion layer formed from the surface of the substrate of the semiconductor chip has a low reflectance that is substantially exposed to the incident light, and the surface of the diffusion layer coated on the central part of the surface of the diffusion layer that is exposed to the incident light is A sign for automatic bonding of semiconductor chips consisting of a highly reflective metal film. (2) Utility model registration Claim 1. The mark for automatic bonding of semiconductor chips, characterized in that the diffusion layer as the mark is an n-type layer in which phosphorus is diffused at a high concentration. (3) A mark for automatic bonding of a semiconductor chip, as set forth in Claim 1 of the Utility Model Registration Claim, characterized in that the surface of the substrate around the surface of the diffusion layer serving as the mark is covered with a silicon oxide film. (4) A sign for automatic bonding of semiconductor chips, characterized in that the metal film is an aluminum film in the sign set forth in claim 1 of the utility model registration claim. (5) A mark for automatic bonding of semiconductor chips, characterized in that the mark is protected by a silicon nitride film in the mark according to claim 1 of the utility model registration claim.
JP1987102521U 1987-07-03 1987-07-03 Pending JPS648733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987102521U JPS648733U (en) 1987-07-03 1987-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987102521U JPS648733U (en) 1987-07-03 1987-07-03

Publications (1)

Publication Number Publication Date
JPS648733U true JPS648733U (en) 1989-01-18

Family

ID=31332503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987102521U Pending JPS648733U (en) 1987-07-03 1987-07-03

Country Status (1)

Country Link
JP (1) JPS648733U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0851113A (en) * 1994-08-05 1996-02-20 Sony Corp Semiconductor integrated circuit and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0851113A (en) * 1994-08-05 1996-02-20 Sony Corp Semiconductor integrated circuit and manufacturing method thereof

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