JPH0878593A - Chip carrier and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a chip carrier which can be thinned in its entirety and which does not require a bonding step with external connection terminals such as a lead frame. [Structure] The chip carrier 1 uses a conductor plate as a support substrate 2 in place of an insulating substrate such as a glass epoxy substrate, and on the support substrate 2, insulating layers 3, 5 and conductor layers 4, 4 are provided. A laminated portion 7 formed by sequentially stacking 6 is provided. Further, after the laminated portion 7 is provided, the leads 8 formed by etching the support substrate 2 on the opposite surface while the conductor pattern of the laminated portion 7 is protected are obtained. After the laminated portion 7 is formed on the support substrate 2 in this manner, the support substrate 2 is processed into external connection terminals such as the leads 8. Therefore, the conventional support substrate is eliminated and the thickness of the chip carrier 1 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier on which a semiconductor integrated circuit device can be mounted and which has an external connection terminal for connecting to an external circuit, and a method for manufacturing the chip carrier.

More specifically, the present invention has a laminated portion having a structure in which insulating layers and conductor patterns are alternately stacked and has a quad flat package type external connection terminal for connecting to an external circuit. The present invention relates to a chip carrier for semiconductor packages.

Further, according to the present invention, a conductor plate is used as a supporting substrate such as an insulating layer, and an insulating layer, a conductor pattern,
The present invention relates to a method of manufacturing a chip carrier in which an insulating layer and a conductor pattern are alternately stacked to form a laminated portion, and then the conductor plate of the support substrate is processed to form a conductor pattern that is an external connection terminal.

[0004]

2. Description of the Related Art A semiconductor device of this type is generally one in which a semiconductor integrated circuit element (IC chip) is mounted on a chip carrier and these are molded with resin.

Among the chip carriers, a quad flat package (hereinafter referred to as "QF")
The "P" type structure required a supporting substrate for supporting the insulating layers and the conductor patterns in order to stack them alternately. Then, after forming all the necessary insulating layers and conductor patterns on the supporting substrate, a separately prepared lead frame is joined and integrated by a method such as soldering.

On the other hand, as a form different from the above-mentioned chip carrier, the outer lead portion of the lead frame is covered with a sheet, and the prepreg and the copper foil are bonded to the whole, and the conductor pattern is formed in the same manner as the so-called multilayer printed wiring board construction method. It is proposed that the sheet of the outer lead portion and the insulating layer on the sheet are finally removed and the outer lead is exposed to form a chip carrier.

[0007]

However, since the chip carrier prepared by the former method originally has an unnecessary supporting substrate, the chip carrier becomes thicker by the thickness of the supporting substrate, and this chip carrier is used. There is a drawback that the semiconductor package becomes thick.

Similarly, in the chip carrier obtained by the former method, the supporting substrate itself is costly, and a step of joining the inner lead of the lead frame and the laminated portion is required, which is also costly, and the semiconductor package There was a drawback that it drastically increased the overall cost.

On the other hand, in the chip carrier produced by the latter method, the step of covering the outer lead portion of the lead frame with a sheet and finally the step of removing the sheet and the insulating layer on the sheet are complicated, There is a drawback in that the ratio of the insulating layer that becomes unnecessary later is large, which increases the cost.

It is an object of the present invention to solve the above-mentioned drawbacks, to reduce the overall thickness, and to provide a chip carrier in which a step of joining with an external connection terminal such as a lead frame is omitted, and a manufacturing method thereof. .

[0011]

In order to achieve the above-mentioned object, in the invention according to claim 1, a laminated portion constituted by laminating an insulating layer and a conductor layer at a predetermined position of a supporting substrate made of a conductor plate. And an external connection terminal such as a lead frame formed by processing the conductor plate into a predetermined shape.

The conductor plate according to claim 2 has a thickness of 35 μm to 30 μm.
It is a metal plate having a thickness of 0 μm and a hardness of 150 to 300 HV.

A conductor plate according to a third aspect is characterized by being an iron-nickel alloy.

The conductor plate according to claim 4 has a hardness of 150 HV.
It is characterized by being the above copper alloy.

In order to achieve the above object, in the invention according to claim 5, an insulating layer is formed on the conductor plate of the supporting substrate, and a through hole is formed in the insulating layer according to a predetermined wiring pattern, and the through hole is formed. A conductor is provided and a conductor pattern is provided on the insulating layer with a predetermined wiring pattern, and these steps are repeated a predetermined number of times to form a laminated portion, and then the conductor plate is processed to form an external connection terminal such as a lead frame. It is characterized by doing.

[0016]

According to the first aspect of the present invention, a conductor plate is used as a supporting substrate in place of an insulating substrate such as a glass epoxy substrate, and an insulating layer and a conductor layer are sequentially stacked on the supporting substrate. A laminated portion is provided. Further, after the laminated portion is provided, the surface on the opposite side of the support substrate is etched according to a predetermined pattern while the conductor layer of the laminated portion is protected to form an external connection terminal such as a lead frame. After forming the laminated portion on the support substrate in this manner, the support substrate itself is processed into an external connection terminal such as a lead frame.
The chip carrier becomes thinner.

The conductor plate according to claim 2 is 35 μm to 30 μm.
Since it is a metal plate having a thickness of 0 μm and a hardness of 150 to 300 HV, it is easy to form an external connection terminal such as a lead frame and has sufficient strength as a lead frame.

Since the conductor plate according to the third or fourth aspect is an iron-nickel alloy or a copper alloy having a hardness of 150 HV or more, it is easy to form an external connection terminal such as a lead frame and has sufficient strength as a lead frame. Have.

According to a fifth aspect of the present invention, an insulating layer is formed on the conductor plate of the supporting substrate, and then a through hole is formed in the insulating layer according to a predetermined wiring pattern. Further, a conductor plate is used to provide a conductor having the same thickness as the insulating layer in the through hole by electroplating or the like. A conductor pattern having a predetermined wiring pattern is provided on the insulating layer. These steps are repeated a predetermined number of times to form a laminated portion. As a result, a laminated portion having a predetermined wiring is obtained. Next, the conductor plate is etched into a predetermined pattern to form external connection terminals such as a lead frame. As a result, an external connection terminal such as a lead frame connected to the wiring of the laminated portion can be obtained, and the supporting substrate is changed to an external connection terminal such as a lead frame, so that the thickness of the entire chip carrier is reduced and the lead frame is also reduced. The step of connecting the components becomes unnecessary.

[0020]

The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a rear view showing an embodiment of the chip carrier of the present invention. FIG. 2 is a front view showing the same embodiment. FIG. 3 is a sectional view of FIG.

In these figures, the chip carrier 1
Is formed, for example, by laminating insulating layers 3 and 5 and conductor layers 4 and 6 at predetermined positions on a supporting substrate 2 made of an iron-nickel alloy conductor plate having a plate thickness of about 125 μm. It includes a laminated portion 7, an area 9 in which the conductor plate 2 is processed into a predetermined shape to form a lead 8, and an island 10. That is, in FIG. 1, long groove-shaped through holes 11, 11, 11, 11 are formed in the area 9 of the support substrate 2,
The conductor sandwiched between the through holes 12 of each through hole portion 11 is left. Then, for example, by cutting the part of the dotted line A, the chip carrier 1 having the leads 8 is formed as shown in FIG. Areas 13, 13, 13,
Reference numeral 13 is a connecting portion of the electrode terminals of the laminated portion 3. Further, on the laminated portion 7, a semiconductor integrated circuit element (IC chip) 1
It is equipped with 4.

Such a chip carrier 1 is constructed as follows.

[Formation Step of First Layer] First, in this embodiment, the support substrate 2 has, for example, a plate thickness of about 150 μ
m] copper alloy plate 17 is used. The copper alloy plate 17 is washed and dried well (see FIG. 4 (a)).

Then, a photosensitive resin (for example, Provicoat 5000 (trade name); manufactured by Nippon Paint Co., Ltd.) is printed on the copper alloy plate 17 by screen printing so that the thickness after drying is, for example, about 30 μm. After doing, for example, 80
Drying is performed at [degree C] for about 30 minutes, for example. As a result, FIG.
As shown in (b), the resin layer 18 is formed on the copper alloy plate 17.

Next, a glass mask (not shown) is placed on the resin layer 18, and ultraviolet rays are applied from above, for example, about 3000 [m.
J / cm2]. After that, about 1 dedicated developer
Blow for minutes to remove the resin in the area not exposed to UV light. After finishing this process, wash with water, for example, 1
The remaining resin is cured by heating at 40 [degrees C] for 30 minutes, for example. As a result, as shown in FIG.
The insulating layer 3 in which the through holes 19 are provided in the resin layer 18 according to a predetermined wiring pattern is formed on the copper alloy plate 17.

Next, another sample treated in the same manner was prepared, the supporting substrates 2 were overlapped with each other, and the periphery thereof was taped so that the processing liquid did not enter the inside of the supporting substrate 2. At this time, the surfaces 20 and 2 of the copper alloy plate 17 of the support substrate 2 on which the photosensitive resin was not printed were not bonded to each other.
An insulating material serving as a resist may be attached to the surface 1 or the surface 22 where the laminated portion 7 is not provided. In this way, it is permeated into the copper sulfate plating solution and electroplated at a current density of 5 [A / dm @ 2] for, for example, about 25 minutes. As a result, the through hole 19 provided in accordance with the predetermined wiring pattern of the insulating layer 3, that is, the portion of the resin layer 18 from which a part of the resin has been removed is plated with a thickness substantially the same as the thickness of the resin layer 18, and the conductor 24 is formed. To provide. As a result, as shown in FIG.
The conductor 24 is provided in the through hole 19 provided according to the predetermined wiring pattern.

Next, on the surface of the insulating layer 3 having the structure shown in FIG.
After forming a copper thin film of 2 [μm], copper sulfate plating is performed to form a copper film having a thickness of, for example, about 10 [μm]. On such a copper film, for example, a liquid resist (PM
ER (trade name); manufactured by Tokyo Ohka Kogyo Co., Ltd.) is uniformly applied and dried to form a photosensitive layer.

After that, the photosensitive layer was exposed according to a predetermined wiring pattern, and then developed to form an etching resist pattern. Next, after etching with a ferric chloride solution, the etching resist was peeled off. As a result, as shown in FIG. 4E, the conductor layer 4 is formed on the insulating layer 3.

As a result, the insulating layer 3 is formed on the copper alloy plate 17.
Thus, the first layer of the conductor layer 4 is formed.

[Second Layer Forming Step] Again, a photosensitive resin (for example, Probicoat 5) is screen-printed on the conductor layer 4 and the portion of the insulating layer 3 where the conductor layer 4 is not formed.
000 (trade name); manufactured by Nippon Paint Co., Ltd.) is printed so that the thickness after drying is, for example, about 30 [μm], and then dried at, for example, 80 [degrees C] for about 30 minutes to form the resin layer 25. Form.

Next, a glass mask (not shown) is placed on the resin layer 25, and ultraviolet rays are applied from above, for example, about 3000 [m.
J / cm2]. After that, about 1 dedicated developer
Blow for minutes to remove the resin in the area not exposed to UV light. After finishing this process, wash with water, for example, 1
The remaining resin is cured by heating at 40 [degrees C] for 30 minutes, for example. As a result, as shown in FIG.
The insulating layer 5 is formed on the conductor layer 4 and the portion of the insulating layer 3 without the conductor layer 4, and the through hole 26 is provided in the insulating layer 5 according to a predetermined wiring pattern.

Next, it is immersed again in a copper sulfate plating solution and electroplated at a current density of 5 [A / dm2] for, for example, about 25 minutes. Thereby, the through hole 26 provided in accordance with the predetermined wiring pattern of the insulating layer 5, that is, the portion of the resin layer 25 from which a part of the resin is removed is plated with a thickness substantially the same as the thickness of the resin layer 25, and the conductor 27 is formed. To provide. As a result, as shown in FIG. 4 (g), a conductor 27 is provided in the through hole 26 provided according to a predetermined wiring pattern of the insulating layer 5.

Next, on the surface of the insulating layer 5 having the structure shown in FIG.
After forming a copper thin film of 2 [μm], copper sulfate plating is performed to form a copper film having a thickness of, for example, about 10 [μm]. On such a copper film, for example, a liquid resist (PM
ER (trade name); made by Tokyo Ohka Kogyo Co., Ltd.) is uniformly applied and dried to form a photosensitive layer.

After that, the photosensitive layer was exposed according to a predetermined wiring pattern, and then developed to form an etching resist pattern. Next, after etching with a ferric chloride solution, the etching resist was peeled off. As a result, as shown in FIG. 4H, the conductor layer 6 is formed on the insulating layer 5.

As a result, the second layers of the insulating layer 5 and the conductor layer 6 are formed on the conductor layer 4.

Then, the laminated portion 7 including the insulating layers 3 and 5 and the conductor layers 4 and 6 is formed.

[Lead Frame Making Process] Next, an acid resistant sheet is attached to the circuit-formed laminated portion 7,
A dry film was attached to the exposed surface of the support substrate 2 on the back surface. In the same process as above, the pattern to be the lead 8 is exposed and developed, and after etching, the dry film is peeled off to process the support substrate 2 into the lead 8. As a result, the member shown in FIG. 4I or FIG. 1 is formed.

If necessary, in order to increase the adhesive strength between the lead 8 and the insulating layer 3, a resin may be printed on the lead 8 to fix the tip of the lead frame.

Finally, by using a blow-up type plating device, a necessary portion is masked and nickel plating is performed to, for example, about 5 [μ
m] and gold plating, for example, about 0.5 [μm].

According to the embodiment thus constructed, the conductor supporting substrate 2 is used in place of the insulating supporting substrate, and the insulating layers 3 and 5 and the conductor layers 4 and 6 are laminated on the supporting substrate 2, and the laminated portion 7 is formed. And the support substrate 2 of the conductor is formed on the lead 8, the unnecessary thickness of the chip carrier 1 can be reduced, and the same as or better than the conventional product can be achieved without special joining with the lead 8. The chip carrier 1 having the above performance can be obtained, and the overall cost can be reduced.

Further, in the above-mentioned embodiment, since it is not necessary to use a joining material such as solder for joining the inner lead of the lead 8 and the laminated portion 7, not only the cost required for joining is zero but also the joining There is no fear of damage due to heating at the time, and there is no concern of disconnection of the joint portion when the strength of the joint portion is significantly reduced or significantly due to heat when mounting the semiconductor package using this chip carrier 1 on a printed wiring board. Overall reliability is improved.

[Second Embodiment] In the second embodiment, a copper plate (EFTEC64T (trade name)) having a high strength and a thickness of, for example, 150 [μm] is used for the supporting substrate 2. Further, before the resin is applied to the supporting substrate 2, the thickened portion is first etched to finally make it have no protrusion. The process of forming the laminated portion 7 is the same as that of the first embodiment except that the etching of the leads 8 is performed from both sides of the support substrate 2.

[Third Embodiment] FIG. 5 is a rear view showing a third embodiment of the present invention. As shown in FIG. 5, the insulating layer 3a having a large area is formed on the support substrate 2a, and the laminated portion 7a including the conductor layer, the insulating layer, and the conductor layer is formed at a position corresponding to the island 10, and The lead 8a is formed by etching in a predetermined pattern as shown, and the terminal tip of the lead 8a on the outer lead 30 side is formed as a pad-shaped terminal 31. This is similar to the first embodiment.

The third embodiment is configured as described above, so that the area of the resin portion (insulating layer 3) of the chip carrier 1 is widened and the terminals 31 for electrical inspection are provided as shown in the figure. , Electrical inspection after mounting semiconductor devices is now possible.

[0046]

As described above, according to the first aspect of the invention, a laminated portion formed by laminating an insulating layer and a conductor layer at a predetermined position of a support substrate made of a conductor plate, and the conductor plate. Since it has an external connection terminal such as a lead frame that is processed into a predetermined shape, the unnecessary thickness of the chip carrier can be reduced, and it is equivalent to the conventional product without special joining with the lead frame. Since the chip carrier having the above performance can be obtained, the overall cost can be reduced.

Further, in the invention according to claim 1, since it is not necessary to use a joining material such as solder for joining the inner lead of the lead frame, it is possible to eliminate the joining step and to heat the joining. No worries about damage.

When mounting a semiconductor package using the chip carrier according to the first aspect of the present invention on a printed wiring board, there is no fear of deterioration of the strength of the joint portion or disconnection of the joint portion due to the heat, so that the overall reliability is improved. The property is improved.

The conductor plate according to claim 2 is 35 μm to 30 μm.
Since it is a metal plate having a thickness of 0 μm and a hardness of 150 to 300 HV, it is suitable as a supporting substrate, and
It is suitable for forming external connection terminals such as lead frames.

The conductor plate according to claim 3 is an iron-nickel alloy, and thus is suitable as a supporting substrate and also for forming an external connection terminal such as a lead frame.

The conductor plate according to claim 4 has a hardness of 150H.
Since it is a copper alloy of V or more, it is suitable as a supporting substrate and also suitable for forming an external connection terminal such as a lead frame.

According to the fifth aspect of the present invention, an insulating layer is formed on the conductor plate of the supporting substrate, a through hole is formed in the insulating layer according to a predetermined wiring pattern, and a conductor is provided in the through hole. Since a conductor pattern is provided on a layer with a predetermined wiring pattern and these steps are repeated a predetermined number of times to form a laminated portion, the conductor plate is processed to form an external connection terminal such as a lead frame. Since the step of joining the external connection terminals can be eliminated, and the supporting substrate serves as the external connection terminals such as the lead frame, the overall thickness can be reduced.

[0053]

[Brief description of drawings]

FIG. 1 is a back view showing an embodiment of a chip carrier of the present invention.

FIG. 2 is a front view showing an embodiment of the chip carrier.

FIG. 3 is a sectional view of the embodiment.

FIG. 4 is a diagram showing a manufacturing method according to the embodiment.

FIG. 5 is a back view showing the third embodiment.

[Explanation of symbols]

 1 Chip Carrier 2 Support Substrate 3, 5 Insulating Layer 4, 6 Conductor Layer 7 Laminated Part 8 Lead 9 Area 18 Resin Layer

Claims (5)

[Claims] 1. A laminated portion formed by laminating an insulating layer and a conductor layer at a predetermined position on a support substrate made of a conductor plate, and an external connection terminal formed by processing the conductor plate into a predetermined shape. A chip carrier characterized by having. 2. The chip carrier according to claim 1, wherein the conductor plate is a metal plate having a thickness of 35 μm to 300 μm and a hardness of 150 to 300 HV. 3. The chip carrier according to claim 1, wherein the conductor plate is an iron-nickel alloy. 4. The chip carrier according to claim 1, wherein the conductor plate is a copper alloy having a hardness of 150 HV or more. 5. An insulating layer is formed on a conductor plate of a supporting substrate, a through hole is provided in the insulating layer according to a predetermined wiring pattern, a conductor is provided in the through hole, and a predetermined wiring pattern is formed on the insulating layer. A method for manufacturing a chip carrier, which comprises providing a conductor pattern, repeating these steps a predetermined number of times to form a laminated portion, and then processing the conductor plate to form an external connection terminal.