JPH09198250A - Storage method and device - Google Patents

Abstract

(57) Abstract: A storage device suitable for pipeline processing is provided. RAM for pipeline processing A to D
Data is sequentially read from 103, and latches 210 to 21
Latch to 3. By changing the latch order, the processing order of the pipeline processing can be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage method and device for temporarily storing data read from a memory.

[0002]

2. Description of the Related Art In an information processing system for pipeline processing of a plurality of processes, data required for each process is read in advance according to the processing order, and other storage areas of the memory are stored in other memories. It has been conventionally performed to temporarily store and efficiently perform pipeline processing.

[0003]

However, in the above-mentioned conventional example, when the processing order of the pipeline processing is changed on the way, the order in which the data is temporarily stored corresponds to the processing order. Without doing so, the processing efficiency may decrease. SUMMARY OF THE INVENTION It is therefore an object of the present invention to propose a storage method and device that can cope with changes in the processing order of pipeline processing and eliminate useless overhead.

[0004]

In order to achieve such an object, the invention of claim 1 comprises a first storage means for storing data, and a means for reading the data from the first storage means. The second storage means and the control means for variably setting the writing order of the data sequentially read by the reading means into the second storage means.

According to a second aspect of the present invention, the data stored in the first storage means is data used in pipeline processing, and the control means corresponds to the processing order of the pipeline. It is characterized in that the writing order to the second storage means is variable.

According to a third aspect of the present invention, the second storage means is composed of a plurality of latch circuits, and the data is sequentially stored in the plurality of latch circuits according to the writing order set by the control means. It is characterized by

According to a fourth aspect of the present invention, the control means is composed of a counter and a connection changing circuit, the write order to the plurality of latch circuits is determined in correspondence with the count value of the counter, and the first storage It is characterized in that the write order is changed by changing the latch circuit for supplying the data read from the means by the connection changing circuit.

According to a fifth aspect of the present invention, in a storage method of reading data stored in the first memory for pipeline processing and sequentially writing the data in the second memory, the storage method corresponds to the processing order of the pipeline. Then, the writing order of the data to the second memory is variably set.

According to the present invention, the order of writing the read data is changed so that the order of the pipeline processing can be changed.

Further, according to the invention of claim 3, the device can have a simple structure by using the latch circuit as the second data storage means.

Further, according to the invention of claim 4, the apparatus can have a simple structure by using the counter as the control means.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is an example of a configuration diagram of an embodiment of the present invention. Reference numeral 101 is a CPU (central processing unit). 10
Reference numeral 2 denotes a ROM (read only memory) that stores the control program of the CPU 101 and various data. A RAM (random access memory) 103 stores various data. Reference numeral 104 denotes a DMAC (Direct Memory Access Controller) that directly controls access to the memory without going through the CPU 101. 105 is the DMAC 104
Is a temporary storage unit for reading out and temporarily storing necessary data on the RAM 103 by the processes (circuits) A to D 106 to 109. The feature of the present invention lies in the internal configuration of the temporary storage unit 105. The processing circuits 106 to 109 are functional modules that are in charge of a certain process, and use data latched in the temporary storage unit 105.
It is assumed that pipeline processing as shown in (1) of FIG. 3 is performed. Here, it is assumed that each processing time is the same. FIG. 2 shows details of the temporary storage unit 105. In FIG. 2, reference numeral 202 is a DMA interface (I / F) for interfacing the DMAC 104. DMA I / F
Data request signal (DREQ) is output from 20 and DMA
The C 104 waits for the data to be read from the RAM 103 and returns the data establishment signal ACK.

The DMA I / F 202 generates a latch pulse for latching data in the temporary storage latches 210 to 213 in response to the ACK signal. Further, the DMA I / F 202 of the data request source sends the request end signal (LA
When ST) is returned, it is assumed that the DMAC 104 side recognizes that one request has been completed. In FIG. 2, circuits 203 to 217 are features of the present invention.

214 to 217 are Lat of 210 to 213
It is a flag circuit that indicates the presence or absence of valid data for chA to D, and is composed of flip-flops FA to FD. First, before starting the processing circuits A to D of 106 to 109, clear signals CLRA to
The CLRD signal is output for initialization. When the flag is initialized, the DMA I / F 20 is passed through the gate circuit 203.
2 is supplied with a data request signal (REQ), whereby a handshake is performed between the DMA I / F 202 and the DMAC 104.

Reference numeral 204 denotes a connection change circuit, which determines whether or not each request signal REQA-D input to the priority circuit 205 should be connected. Processing order ABC in (1) of FIG.
When the pipeline processing is configured by D, the inputs 1 to 4 to the priority circuit 205 are 1 = A, 2 = B,
3 = C and 4 = D. First, 210 with the highest priority
LatchA is selected to latch the data for the first request. At this time, when the mth data is latched in LatchA of 210, the flag FA of 214 is set. Here, m is the number of accesses for one request.

In the present embodiment, for the purpose of explanation, m = 1
Although it is assumed that the access is made only once, if, for example, the request is accessed four times, m = 4,
Four latch pulses will be generated, and Latc will be generated.
hA is a 4 × n (data bus width) bit latch group. In this case, the flip-flop FA will be set by the generation of the m = 4th latch pulse. Thereafter, latch B, C, and D are sequentially latched by the same operation. Here, when each processing is completed, each CLR signal is issued and each flag circuit is reset. As a result, the data request signal REQ is again generated in the gate circuit 203, and the same cycle as described above is repeated. Here, as shown in FIG. 3, consider a case where the pipeline processing order changes from (1) to (2) at a certain time. In this case, in the conventional latching order, the pipeline processing order and the latching order do not engage with each other, resulting in an overhead and a decrease in processing efficiency. Therefore, at this time, the connection changing circuit 204 switches the latch order to BDAC. This makes it possible to remove this overhead.

FIG. 4 shows a specific example of the connection changing circuit. There are four selectors (401 to 404) with R = 4 to 1. Here, k is the number of processes constituting the pipeline process. In this example, R = 4. In these selectors, the connection order to the priority circuit of the next stage is switched by changing the values of the selection signals S0 and S1. In FIG. 4, when S0 = 0 and S1 = 0, 1 = A, 2 = B, 3 = C, 4 = D (1 → 4 from the highest priority), but S0 = 0, S1. When = 1 is set, 1 = B, 2 = D, 3 = A, and 4 = C are connected. Furthermore, a combination that cannot be changed only by controlling S0 and S1 in FIG. 4, such as ABCD → ABDC, is (40
1, 402), (403, 404) in pairs,
A method of controlling the selection signal or controlling the selection signal independently of each selector is also conceivable.

(Embodiment 2) The example of FIG. 3- (3) is an example in which the time width of each process is different. In this case, even if the process A ends, the data of the process D is still Lat.
It may not be latched to chD. At this time, S is assigned each time the highest priority one is latched.
There is also a method of switching 0 and S1 and sequentially changing the remaining unlatched ones to the highest priority. For example, when LatchA is latched, the priority is changed from ABCD to BCDA, and when LatchB is latched, the priority is changed from BCDA to CDAB.

(Embodiment 3) FIG. 5 is a block diagram for explaining the present invention. The basic part is shown in FIG. 2 described in the first embodiment.
Is the same as However, here, instead of using the priority circuit, the counter circuit (504) is used to realize the same function. When the pipeline processing has four configurations A, B, C, and D as in the example, any counter circuit can be used as long as it can express four transition states. For example, a binary counter, a Johnson counter, a Gray code counter, etc.

Decoding the outputs of those counters,
A circuit 504 is a circuit that repeatedly moves four states 0 → 1 → 2 → 3 in order. At this time, each flag circuit FA to FD
Is set by the clock, that is, by the m-th latch pulse, the state transits. The connection changing circuit 505 is the same as that in the first embodiment. When S0 = 0 and S1 = 1, the states are 0 = A, 1 = B, 2 = C, and 3 = D. Here, when the processing order of the pipeline is changed from (1) to (2) as shown in FIG. 3, S0 = 0 and S1 = 1 are set,
The wasteful overhead is removed by changing the states 0 = B, 1 = D, 2 = A, 3 = C.

[0021]

As described above, according to the present invention,
Even if the processing order in the pipeline processing is changed, the order in which the data required for each processing is latched can be changed in accordance with the change, and wasteful overhead can be removed and efficient processing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a temporary storage unit 105.

FIG. 3 is an explanatory diagram showing a pipeline processing order.

FIG. 4 is a circuit diagram showing a configuration of a priority circuit 205.

FIG. 5 is a circuit diagram showing a configuration of a third embodiment.

[Explanation of symbols]

 101 CPU 102 ROM 103 RAM 104 DMAC 105 Temporary Storage Unit 106 to 109 (Pipeline) Processing A to D

Claims (5)

[Claims] 1. A first storage means for storing data, a means for reading data from the first storage means, a second storage means, and the first storage means for sequentially reading data from the reading means. A storage device comprising: a control unit that variably sets the writing order of the second storage unit. 2. The data stored in the first storage means is data used for pipeline processing, and the control means stores data in the second storage means in association with a processing order of the pipeline. 2. The storage device according to claim 1, wherein the writing order of is changed. 3. The second storage means is composed of a plurality of latch circuits, and the data is sequentially stored in the plurality of latch circuits according to the writing order set by the control means. The storage device according to claim 1. 4. The control means is composed of a counter and a connection change circuit, and corresponds to the count value of the counter,
The write order to the plurality of latch circuits is determined, and the first
4. The storage device according to claim 3, wherein the writing order is changed by changing the latch circuit that supplies the data read from the storage means by the connection changing circuit. 5. A storage method for reading data stored in a first memory for pipeline processing and sequentially writing the data in a second memory, wherein the data of the data is stored in correspondence with a processing order of the pipeline. A storage method characterized in that the order of writing to the second memory is variably set.