JPH09288894A - Ferroelectric memory - Google Patents

Abstract

(57) [Abstract] (Correction) [Problem] To speed up the cycle time of a ferroelectric memory adopting a plate selection method, to stabilize the read operation of a large capacity ferroelectric memory, and to reduce its power consumption. Try. SOLUTION: Plate lines VPL0 to VPL7 are set to a valid level before a selection operation of a designated word line is started, and set to an invalid level after this word line is deselected, and plate lines VPL0 to VPL0 are set. The effective level of VPL7 is set to the level of the binary read signal on the bit line, that is, the intermediate potential HVC between the power supply voltage VCC and the ground potential VSS, and its invalid level is set to the power supply voltage VCC or the ground potential VSS which is the precharge potential of the bit line. And In addition, the memory array of the ferroelectric memory is, for example, n
+1 set of complementary bit lines B00 * to B0n * to B70
Dividing into a plurality of memory array blocks MAB0 to MAB7 in units of * to B7n *, and corresponding plate lines VP
L0 to VPL7 are selectively activated by setting them to an effective level such as the intermediate potential HVC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, for example, a ferroelectric non-volatile RAM (random access memory) and a shadow RAM, and a technique particularly effective when used for speeding up and low power consumption thereof. It is a thing.

[0002]

2. Description of the Related Art Ferroelectric capacitors and address selection M
A memory array is basically formed by arranging ferroelectric memory cells including an OSFET (metal oxide semiconductor field effect transistor; generically referred to as an insulated gate field effect transistor in this specification) in a grid pattern. There is a ferroelectric memory as a constituent element. Further, there is a so-called ferroelectric non-volatile RAM that operates the ferroelectric memory exclusively in a non-volatile mode. During normal operation, the plate potential of the ferroelectric capacitor and the pre-charge potential of the bit line are set between the power supply voltage and the ground potential. There is a shadow RAM that operates in a volatile mode as a potential and operates in a non-volatile mode when the power is turned off.

The shadow RAM has a recall mode for shifting from the nonvolatile mode to the volatile mode. Further, the ferroelectric non-volatile RAM and the shadow RAM each include a sense amplifier including a unit amplifier circuit provided corresponding to each bit line, and these unit amplifier circuits are connected to a common source line with an operating power supply, that is, a power supply voltage. When the ground potential is selectively supplied, the operating states are selectively and simultaneously performed.

On the other hand, in the ferroelectric memory, the plates of the ferroelectric memory cells arranged in a predetermined number of rows or columns are commonly coupled to corresponding plate lines, and these plate lines are selectively set to effective levels. By doing so, there is a so-called plate selection method in which a corresponding predetermined number of ferroelectric memory cells are selectively brought into a selected state. In this plate selection method, each bit line of the memory array is precharged to the power supply voltage or the ground potential, and the selection level of the plate line is set to the ground potential different from the precharge potential of the bit line in order to obtain a sufficient signal amount. Alternatively, the power supply voltage is used.

[0005]

As is well known, the read operation in the nonvolatile mode of the ferroelectric non-volatile RAM and the read operation in the recall mode of the shadow RAM reverse the polarization state of the selected ferroelectric memory cell. This is so-called destructive read in which the read is performed, and after the read is completed, rewrite is necessary to restore the polarization state of the selected ferroelectric memory cell. Therefore, when the ferroelectric non-volatile RAM or the shadow RAM adopts the plate selection method, the selection plate line made to be an effective level such as the ground potential or the power supply voltage from the precharge potential such as the power supply voltage or the ground potential is a word. Before the line is brought into the non-selected state, it is necessary to return it to the original precharge potential and rewrite the selected memory cell by utilizing the binary read signal established on the bit line. That is, when the plate selection method is adopted, it is necessary to wait for a predetermined period from the time when the plate line is returned to the precharge potential until the time when sufficient rewriting is performed, and the plate line potential is fixed. Compared with the normal word line selection method, the cycle time of the ferroelectric non-volatile RAM and shadow RAM becomes longer, and the machine cycle of the system including this is restricted.

On the other hand, during the read operation of the ferroelectric non-volatile RAM in the non-volatile mode and the read operation of the shadow RAM in the recall mode, the unit amplifier circuits of the sense amplifiers are simultaneously operated as described above. Further, in recent years, the capacity of the ferroelectric memory has been remarkably increased, and along with this, the number of unit amplifier circuits of the sense amplifiers which are operated simultaneously is also increasing. As a result, the power supply noise of the ferroelectric non-volatile RAM and shadow RAM increases, and the read operation becomes unstable, and at the same time, the ferroelectric non-volatile RAM and shadow RA.
The operating current in the read operation of M and the like increases, which hinders the reduction of power consumption.

An object of the present invention is to speed up the cycle time of a ferroelectric memory adopting a plate selection system and speed up the machine cycle of a system including the ferroelectric memory. Another object of the present invention is to stabilize the read operation of a ferroelectric memory having a large capacity and to reduce its power consumption.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a ferroelectric memory such as a ferroelectric non-volatile RAM and a shadow RAM adopting the plate selection method, the plate line is set to an effective level before the selection operation of the designated word line is started, and this word line is After being deselected, it becomes an invalid level,
The effective level of the plate line is an intermediate potential between the high level and the low level after amplification of the binary read signal on the bit line, that is, the power supply voltage and the ground potential, and the invalid level thereof is the power supply voltage which is the precharge potential of the bit line. Or set to ground potential. Further, a memory array such as a ferroelectric non-volatile RAM and a shadow RAM is divided into a plurality of memory array blocks, for example, with a predetermined number of bit lines as a unit, and these memory array blocks are set to corresponding plate lines as effective levels. As a result, the sense amplifier is selectively activated, and the sense amplifier is divided into a plurality of sense amplifier blocks corresponding to the memory array blocks and selectively activated together with the corresponding memory array blocks.

According to the above means, only the designated word line is brought into the selected state, in other words, the plate line is brought to the valid level or the invalid level while the designated word line is brought into the selected state. Without rewriting non-volatile data to the selected ferroelectric memory cell, and selectively activating only the sense amplifier block corresponding to the specified memory array block, the ferroelectric nonvolatile RAM and shadow It is possible to reduce the required operating current during the non-volatile read operation of the RAM or the like. As a result, the cycle time of the ferroelectric non-volatile RAM and shadow RAM adopting the plate selection method can be shortened, the machine cycle of the system including the same can be shortened, and the capacity of the ferroelectric non-volatile RAM can be increased. Noise can be suppressed by suppressing power supply noise of the static RAM and shadow RAM, and the power consumption thereof can be reduced.

[0011]

1 is a block diagram showing an embodiment of a ferroelectric non-volatile RAM (ferroelectric memory) to which the present invention is applied, and FIG. A block diagram of one embodiment of a memory array MARY and a sense amplifier SA included in a dielectric nonvolatile RAM is shown. Based on these figures, first, an outline of the configuration and operation of the ferroelectric nonvolatile RAM of this embodiment will be described. The circuit elements forming each block in FIGS. 1 and 2 are not particularly limited, but are formed on one semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

In FIG. 1, the ferroelectric non-volatile RAM of this embodiment has a memory array MARY arranged as a basic constituent element which occupies most of the semiconductor substrate area. As illustrated in FIG. 2, the memory array MARY has m + 1 word lines W0 arranged in parallel in the vertical direction of the drawing.
~ Wm and a total of 8x arranged in parallel to the horizontal direction of the figure
(N + 1) sets of complementary bit lines B00 * to B0n * to B70 * to B7n * (here, for example, the non-inverted bit line B
00T and the inversion bit line B00B are collectively denoted by * like a complementary bit line B00 *. In addition, a so-called non-inverted bit line or the like which is selectively set to high level when it is enabled is represented by adding T to the end of the name, and when it is enabled, it is selectively set to low level. For inverted bit lines etc. that are written, B is added at the end of the name.
It is indicated by adding. The same applies hereinafter). At the intersections of these word lines and complementary bit lines, a total of 8 × (m + 1) ×
(N + 1) pairs of ferroelectric memory cells are arranged in a grid pattern.

In this embodiment, the memory array MAR
Y is divided into eight memory array blocks MAB0 to MAB7 in units of a predetermined number, that is, n + 1 sets of complementary bit lines, and these memory array blocks are configured (m
The plates of the ferroelectric memory cells of +1) × (n + 1) pairs are commonly coupled to the corresponding plate lines VPL0 to VPL7. In addition, the memory array block MAB0
To complementary bit lines B00 * to B0n * which form to MAB7
Through B70 * to B7n * non-inverted and inverted signal lines,
When the ferroelectric nonvolatile RAM is in the non-selected state, both are precharged to the ground potential VSS or the power supply voltage VCC, and after the amplification operation of the minute read signal by the corresponding unit amplifier circuit of the sense amplifier SA is completed, Either one of them selectively supplies the power supply voltage VCC or the ground potential VS.
S.

On the other hand, the plate lines VPL0 to VPL7 are
Normally, complementary bit lines B00 * to B0n * to B70 *
When the ferroelectric non-volatile RAM is brought into a selected state by setting the precharge potential of B7n *, that is, the ground potential VSS or the power supply voltage VCC to the selected state, the Y address signal AYi of the upper 3 bits is set at a predetermined timing. -2 to AYi, the effective level is alternatively set to the intermediate potential HVC. The intermediate potential HVC is set to a substantially intermediate potential between the high level and the low level after amplification of the binary read signal in the complementary bit lines B00 * to B0n * to B70 * to B7n *, that is, between the power supply voltage VCC and the ground potential VSS. It

As a result, when the word lines W0 to Wm are alternatively set to the selected level such as the high voltage VCH, the memory array blocks MAB0 to MAB7 have the corresponding 8 levels.
Address selection M of × (n + 1) pairs of ferroelectric memory cells
The OSFETs are turned on all at once, but the plate line VP
Of L0 to VPL7, only one memory array block corresponding to the plate line at the effective level becomes substantially active, and the minute read signal of the n + 1 pair of ferroelectric memory cells coupled to the selected word line is Corresponding n +
It is output to a pair of complementary bit lines. Plate line VPL0
Of the VPL7, the seven memory array blocks corresponding to the plate line at the invalid level are not activated because the invalid level of the plate line and the precharge potential of the corresponding complementary bit line are the same potential. , No read operation is performed.

As described above, in the ferroelectric non-volatile RAM of this embodiment, the so-called plate in which the memory cells in the memory array block are selected by the plate lines VPL0 to VPL7 in accordance with the selection in the row unit by the word lines W0 to Wm. A selection method is adopted, and n + 1 is connected to a specified word line from a specified one memory array block.
The ferroelectric memory cells are selectively brought into a selected state.
The specific configuration of the memory array MARY is as follows.
Details will be described later.

The word lines W0 to Wm forming the memory array MARY have X address decoders X below them.
D and, alternatively, the selection level. The X address decoder XD has i + 1 from X address latches XL.
The bit internal address signals X0 to Xi are supplied, and the clock generation circuit CG supplies the internal control signal XG. The X address latches XL are supplied with X address signals AX0 to AXi from the address input terminals A0 to Ai via the address buffer AB in a time division manner.
The internal control signal XL is supplied from the clock generation circuit CG.

The X address latch XL has an address input terminal A when the ferroelectric nonvolatile RAM is selected.
The X address signals AX0 to AXi input from 0 to Ai via the address buffer AB are fetched and held according to the internal control signal XL, and the internal address signals X0 to Xi are formed based on these X address signals. X
It is supplied to the address decoder XD. Further, the X address decoder XD is selectively brought into an operating state when the internal control signal XG is set to the high level, and the internal address signal X0
To Xi are decoded and one of the corresponding word lines W0 to Wm of the memory array MARY is selectively set to a selection level such as the high voltage VCH. The high voltage VCH is a positive potential higher than the power supply voltage VCC by at least the threshold voltage of the address selection MOSFET of the ferroelectric memory cell.

Next, the complementary bit lines forming the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SA. The sense amplifier SA is supplied with a precharge control signal PC, common source line signals CSP0 to CSP7 and CSN0 to CSN7 from the clock generation circuit CG, and a predetermined precharge voltage VPC from an internal voltage generation circuit (not shown). It The precharge control signal PC is at a high level like the power supply voltage VCC when the ferroelectric nonvolatile RAM is in the non-selected state, and when the ferroelectric nonvolatile RAM is in the selected state, the predetermined level. It is set to a low level like the ground potential VSS at the timing. Also, common source line signals CSP0 to
Normally, CSP7 and CSN0 to CSN7 are set to an invalid level such as the ground potential VSS or the power supply voltage VCC, and when the ferroelectric nonvolatile RAM is in the selected state, the power supply voltage VCC is alternatively set at a predetermined timing. Alternatively, it is set to an effective level such as the ground potential VSS. The precharge voltage VPC is set to the ground potential VSS when the ferroelectric non-volatile RAM adopts the VSS precharge method,
When the C precharge method is adopted, it is set to the power supply voltage VCC.

As shown in FIG. 2, the sense amplifier SA includes a memory array block M of the memory array MARY.
It is divided into eight sense amplifier blocks SAB0 to SAB7 corresponding to AB0 to MAB7. The sense amplifier blocks SAB0 to SAB7 are connected to the complementary bit lines B00 * to B0n of the memory array blocks MAB0 to MAB7.
N to be provided corresponding to * to B70 * to B7n *
Each unit circuit is provided with a unit amplifier circuit in which a pair of CMOS (complementary MOS) inverters are cross-coupled to each other and three N-channel MOSFETs are connected in series and parallel. And a bit line precharge circuit.

Sense amplifier blocks SAB0 to SAB7
Amplification M of the unit amplification circuit of the n + 1 unit circuits constituting the
The source of the OSFET is the corresponding common source line CSP.
0 and CSN0 to CSP7 and CSN7, respectively. Further, the complementary input / output node of the unit amplifier circuit of each unit circuit corresponds to the corresponding complementary bit line B00 of the memory array blocks MAB0 to MAB7 on the right side of the drawing.
* To B0n * to B70 * to B7n *, respectively, and are commonly coupled to the non-inverted or inverted signal line of the complementary common data line CD * via a pair of corresponding switch MOSFETs on the left side of the drawing. . The precharge control signal PC is commonly supplied from the clock generation circuit CG to the gates of the three precharge MOSFETs forming the bit line precharge circuit of each unit circuit,
The gate of the switch MOSFET of each unit circuit has a corresponding bit line selection signal YS from the Y address decoder YD.
00 to YS0n to YS70 to YS7n are supplied.

As a result, the sense amplifier block SAB
The three precharge MOSFETs forming the bit line precharge circuit of each unit circuit of 0 to SAB7 are selectively turned on all at once in response to the high level of the precharge control signal PC, and the memory of the memory array MARY. The non-inverted and inverted signal lines of the corresponding complementary bit lines B00 * to B0n * to B70 * to B7n * of the array blocks MAB0 to MAB7 are connected to the ground potential VSS or the power supply voltage VC.
Precharge to C. Further, the unit amplifier circuit of each unit circuit has a corresponding common source line signal CSP0 and CSN.
0 to CSP7 and CSN7 are selectively and simultaneously activated by setting the power supply voltage VCC or the ground potential VSS to an effective level, and n + 1 pairs of n + 1 pairs are connected to the selected word line of the memory array MARY. Corresponding complementary bit lines B00 * to B0n * from the ferroelectric memory cell
Through B70 * to B7n * are respectively amplified to amplify a minute read signal to a high level (first level) such as the power supply voltage VCC or a low level (second level) such as the ground potential VSS. This is a binary read signal. Further, the switch MOSFETs of each unit circuit have bit line selection signals YS00 to YS0n to YS70 to YS.
Upon receiving the S7n high level, it is selectively turned on, and the memory array blocks MAB0 to MAB0 of the memory array MARY
MAB7 complementary bit lines B0 * to Bn * 0 to B70
* To B7n * corresponding bit and complementary common data line CD
* Is selectively connected.

As described above, the memory array block MA
B0 to MAB7 are alternatively activated, and the common source lines CSP0 and CSN0 to CSP7 and CSN7.
Is alternatively set to an effective level such as the power supply voltage VCC or the ground potential VSS. Therefore, the sense amplifier blocks SAB0 to SAB7 of the sense amplifier SA are alternatively activated together with the corresponding memory array blocks MAB0 to MAB7, and the n + 1 unit amplifying circuits amplify the read signal. The specific configuration and operation of the sense amplifier SA will be described later in detail.

The Y address decoder YD has an i + 1-bit internal address signal Y0 to Y0 from the Y address latch YL.
Yi is supplied, and the internal control signal YG is supplied from the clock generation circuit CG. The Y address latches YL are time-divisionally supplied with Y address signals AY0 to AYi from the address input terminals A0 to Ai via the address buffer AB, and the internal control signal Y from the clock generation circuit CG.
L is supplied.

The Y address latch YL has an address input terminal A when the ferroelectric nonvolatile RAM is selected.
Y address signals AY0 to AYi supplied from 0 to Ai via the address buffer AB are fetched and held in accordance with the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals, Y
It is supplied to the address decoder YD. Further, the Y address decoder YD receives the high level of the internal control signal YG and is selectively brought into an operating state, so that the internal address signals Y0 to Yi.
Of the bit line selection signals YS00 to YS
0n to YS70 to YS7n as an alternative to the power supply voltage VC
Set to high level of C.

The complementary common data line CD * is coupled to the main amplifier MA, which includes a write amplifier and a read amplifier. Of these, the input terminal of the write amplifier is coupled to the output terminal of the input buffer IB, and the output terminal thereof is coupled to the complementary common data line CD *. Also, the input terminal of the read amplifier is the complementary common data line CD *
, Whose output terminal is coupled to the input terminal of the output buffer OB. The input terminal of the input buffer IB is coupled to the data input terminal Din, and the output terminal of the output buffer OB is coupled to the data output terminal Dout. The write amplifier of the main amplifier MA is supplied with an internal control signal WC (not shown) from the clock generation circuit CG, and the output buffer OB is supplied with the internal control signal OC.

The input buffer IB is a ferroelectric nonvolatile R
When the AM is selected in the write mode, the write data input via the data input terminal Din is fetched and transmitted to the write amplifier of the main amplifier MA.
At this time, the write amplifier of the main amplifier MA is selectively activated by receiving the high level of the internal control signal WC, and after the write data transmitted from the input buffer IB is converted into a predetermined complementary write signal, the complementary common signal is supplied. Data line C
D * via the sense amplifier SA to the memory array MAR
Write to a selected pair of ferroelectric memory cells in Y.

On the other hand, the read amplifier of the main amplifier MA is the selected one of the memory array MARY when the ferroelectric nonvolatile RAM is selected in the read mode.
A read signal output from the pair of ferroelectric memory cells via the sense amplifier SA and the complementary common data line CD * is amplified and transmitted to the output buffer OB. At this time, the output buffer OB is selectively activated by receiving the high level of the internal control signal OC, and outputs the read signal transmitted from the read amplifier of the main amplifier MA to the data output terminal D.
The data is output from out to the outside of the ferroelectric nonvolatile RAM.

In the clock generation circuit CG, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a write enable signal WEB which are start control signals are supplied from an external access device through external terminals RASB, CASB, WEB and OEB. The output enable signal OEB is supplied to each. The clock generation circuit CG selectively forms the various internal control signals and the like on the basis of these activation control signals and supplies them to the respective parts of the ferroelectric nonvolatile RAM.

FIG. 3 shows the ferroelectric nonvolatile RAM of FIG.
Memory array MARY and sense amplifier SA included in
A partial schematic diagram of one embodiment is shown. With reference to the figure, a concrete configuration and operation of the memory array MARY and the sense amplifier SA of the ferroelectric non-volatile RAM of this embodiment and its features will be described. In the following description, the memory array block MAB0 and the sense amplifier block SAB0 will be taken as an example.
0 to MAB7 and sense amplifier block SAB0
SAB7 will be described. Also, in the following circuit diagram, the MO with an arrow attached to its channel (back gate) part
The SFET is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 3, the memory array MARY is
Although not particularly limited, n + 1 sets of complementary bit lines B00 *
.About.B0n * to B70 * to B7n *, respectively, and includes eight memory array blocks MAB0 to MAB7 sharing word lines W0 to Wm. Memory array MA
RY is a so-called 2-cell / 2-transistor type array, and complementary bit lines B00 * to B0n * to B70 * to B constituting memory array blocks MAB0 to MAB7.
At the intersections of 7n * and word lines W0 to Wm, (m + 1) × (n + 1) pairs of ferroelectric memory cells each composed of a ferroelectric capacitor Cs and an address selection MOSFET Qs are arranged in a grid pattern.

Memory array blocks MAB0 to MAB7
One electrode of the ferroelectric capacitors Cs of the m + 1 pairs of memory cells arranged in the same column of the complementary bit lines B00 * to B0 via the corresponding address selection MOSFET Qs.
Commonly coupled to the non-inverted or inverted signal lines of n * to B70 * to B7n *, respectively. Further, the gates of the address selection MOSFETs Qs of the n + 1 pairs of memory cells arranged in the same row of each memory array block are commonly coupled to the corresponding word lines W0 to Wm. (M + 1) × (n forming memory array blocks MAB0 to MAB7
The other electrode or plate of the ferroelectric capacitors Cs of the +1) pair of memory cells is connected to the corresponding plate line VPL0.
To VPL7 are commonly coupled.

The word lines W0 to Wm are normally connected to the ground potential V.
Non-selective level like SS, ferroelectric non-volatile R
When AM is selected, internal address signal X
According to 0 to Xi, the selection level such as the high voltage VCH is alternatively set. In addition, the memory array blocks MAB0 to MAB0
MAB7 complementary bit lines B00 * to B0n * to B7
The non-inversion and inversion signal lines of 0 * to B7n * are precharged to, for example, the ground potential VSS by the bit line precharge circuit of the sense amplifier SA described later when the ferroelectric nonvolatile RAM is in the non-selected state. . Further, the plate lines VPL0 to VPL7 are normally set to an invalid level such as the ground potential VSS, and when the ferroelectric non-volatile RAM is set to the selected state, the upper 3 bits of the internal address signal X is set.
According to i-2 to Xi, the effective level such as the intermediate potential HVC is alternatively set.

When the ferroelectric nonvolatile RAM is in the non-selected state, the memory array blocks MAB0 to MAB7 receive the non-selected levels of the word lines W0 to Wm and receive the address selection MOSFETs Qs of all the ferroelectric memory cells.
Is turned off, and all memory array blocks MA
B0 to MAB7 are inactivated.

On the other hand, when the ferroelectric non-volatile RAM is set to the selected state and the word lines W0 to Wm are alternatively set to the selected level, in the memory array blocks MAB0 to MAB7,
The address selection MOSFETs Qs of the corresponding 8 × (n + 1) pairs of ferroelectric memory cells are turned on all at once, and one electrode of the ferroelectric capacitors Cs of these memory cells has a corresponding complementary bit line B00 *. ~ B0n
* To B70 * to B7n * non-inverting and inverting signal lines precharge potential, that is, ground potential VSS or power supply voltage V
CC is transmitted. At this time, the other electrode of the ferroelectric capacitors Cs of these memory cells, that is, the plate line V
PL0 to VPL7 are internal address signals Xi-2 to Xi.
One of the plate lines designated by is set to an effective level such as the intermediate potential HVC, and all the other plate lines are kept at the ground potential VSS. Therefore, one memory array block corresponding to the effective level plate line is activated, and a minute read signal corresponding to the nonvolatile data of the selected n + 1 memory cells is output to each complementary bit line. Since the potentials of both electrodes of the ferroelectric memory cell in the other memory array blocks are the same, the memory array block remains inactive even though the word line is selected. A specific operation in the read mode of the ferroelectric nonvolatile RAM will be described later in detail.

Next, the sense amplifier SA includes eight sense amplifier blocks SAB provided corresponding to the memory array blocks MAB0 to MAB7 of the memory array MARY.
0 to SAB7 are provided. In addition, the sense amplifier block S
AB0 to SAB7 are corresponding memory array blocks M
Each of n + 1 unit circuits provided corresponding to complementary bit lines B00 * to B0n * to B70 * to B7n * of AB0 to MAB7 is provided, and each of these unit circuits includes a P channel MOSFET P1 and an N channel MOSFET N1 and a P channel MOSFET N1. Channel MOSFETP
A pair of C composed of 2 and N-channel MOSFET N2
It includes a unit amplifier circuit in which MOS (complementary MOS) inverters are cross-coupled, and a bit line precharge circuit including three N-channel type precharge MOSFETs N3 to N5.

Sense amplifier blocks SAB0 to SAB7
The gates of the precharge MOSFETs N3 to N5 forming the bit line precharge circuit of each unit circuit of the above are supplied with a predetermined precharge control signal PC from the clock generation circuit CG.
Are commonly supplied, and the precharge voltage VPC is commonly supplied from the internal voltage generation circuit to the commonly connected sources of the precharge MOSFETs N3 and N4. In addition,
The precharge control signal PC is a ferroelectric non-volatile RAM.
Is set to a high level like the power supply voltage VCC when it is in the non-selected state, and is set to a low level like the ground potential VSS at a predetermined timing when it is in the selected state. Further, the precharge voltage VPC is set to the ground potential VSS when the ferroelectric non-volatile RAM adopts the VSS precharge method, and is set to the power supply voltage VCC when adopting the VCC precharge method.

As a result, the precharge M of each unit circuit
When the ferroelectric nonvolatile RAM is in the non-selected state, the OSFETs N3 to N5 are simultaneously turned on in response to the high level of the precharge control signal PC, and the complementary bit lines B00 * to the memory array blocks MAB0 to MAB7.
The non-inverted and inverted signal lines of B0n * to B70 * to B7n * are precharged to the ground potential VSS or the power supply voltage VCC.

On the other hand, sense amplifier blocks SAB0-SB
The sources of the P-channel MOSFETs P1 and P2 forming the unit amplification circuit of the n + 1 unit circuits of the AB7 are commonly coupled to the corresponding common source lines CSP0 to CSP7, respectively, and the sources of the N-channel MOSFETs N1 and N2 are the corresponding common sources. Line CSN0 to CSN7
Are commonly connected to each other. Also, the commonly coupled drains of MOSFETs P1 and N1 and the MOSFETs
The commonly coupled gates of P2 and N2 serve as the non-inverting input / output nodes of the respective unit amplifier circuits, and the corresponding complementary bit lines B00 * to B0n * to B70 * to B7n *.
Connected to the non-inverted signal line of MOSFETs P1 and N1
Of the complementary bit lines B00 * to B0n * to B70 * to B7n * corresponding to the inverted input / output nodes of the unit amplifier circuits. Each connected to a line. The common source line CS
P0 to CSP7 and CSN0 to CSN7 are the common source line signals CSP0 to CSP7 and CSN0.
Needless to say, it corresponds to ~ CSN7.

The common source lines CSP0 to CSP7 and CSN0 to CSN7 are normally ground potential VS, respectively.
When the ferroelectric nonvolatile RAM is set to the selected state such that S or the power supply voltage VCC is set to an invalid level, the power supply voltage VCC or the ground is alternatively selected according to the internal address signals Xi-2 to Xi of the upper 3 bits. It is set to an effective level such as the potential VSS. As a result, the unit amplifier circuits of the n + 1 unit circuits that form the sense amplifier blocks SAB0 to SAB7 have their corresponding common source lines CSP0 to CS
Upon receiving the valid levels of P7 and CSN0 to CSN7, the memory arrays MA are selectively and simultaneously activated.
Memory array block MAB0 in which RY is activated
.About.MAB7 corresponding complementary bit lines B00 * to B0n * to B + 1 from the selected n + 1 ferroelectric memory cells.
The minute read signals output via 70 * to B7n * are respectively amplified to be a binary read signal of a high level such as the power supply voltage VCC or a low level such as the ground potential VSS.

Sense amplifier blocks SAB0 to SAB7
Further, each unit circuit of No. 1 further includes complementary input / output nodes of the unit amplifier circuit, that is, complementary bit lines B00 * to B0n * to B70 * to B7 of the memory array blocks MAB0 to MAB7.
A pair of N-channel type switch MOSFETs N6 provided respectively between n * and the complementary common data line CD *
And N7, respectively. These switch MOSFE
The gates of TN6 and N7 are commonly connected, and Y
The corresponding bit line selection signal Y from the address decoder YD
S00 to YS0n to YS70 to YS7n are supplied, respectively. The bit line selection signals YS00 to YS0
n to YS70 to YS7n are normally all set to a low level like the ground potential VSS, and the ferroelectric nonvolatile R
When AM is selected, it is alternatively set to a high level like power supply voltage VCC at a predetermined timing and in accordance with internal address signals Y0 to Yi.

As a result, the switch MOS of each unit circuit is
The FETs N6 and N7 have corresponding bit line selection signals YS.
00 to YS0n to YS70 to YS7n are selectively set to the high level to selectively turn on, and the sense amplifier blocks SAB0 to SAB of the sense amplifier SA.
The complementary input / output nodes of the corresponding unit circuits of 7, that is, complementary bit lines B00 * to B0n * to B70 * to B7n * and the complementary common data line CD *, that is, the main amplifier MA are selectively connected.

As described above, in the ferroelectric non-volatile RAM of this embodiment, the memory array MARY is the word line W.
Sharing 0 to Wm, n + 1 sets of complementary bit lines B00
8 in units of * to B0n * to B70 * to B7n *
The memory array blocks MAB0 to MAB7 are divided into memory array blocks MAB0 to MAB7 and activated selectively in response to the effective levels of the corresponding plate lines VPL0 to VPL7.
8 sense amplifier blocks SAB0-S corresponding to 7
It is divided into AB7 and the corresponding common source lines CSP0 to
In response to the valid levels of CSP7 and CSN0 to CSN7, they are alternatively activated. Therefore, the capacity of the ferroelectric non-volatile RAM is increasing, and even though a large number of ferroelectric memory cells, that is, unit amplifying circuits are provided in correspondence with the word lines W0 to Wm, they are brought into operation at the same time. The number of unit amplifying circuits is one-eighth of the conventional ferroelectric nonvolatile RAM, that is, n + 1. As a result, the required operating current at the time of the read operation in the nonvolatile mode of the ferroelectric nonvolatile RAM can be reduced, the cost can be reduced, and the power supply noise due to the operation of the sense amplifier can be suppressed. However, the read operation can be stabilized.

FIG. 4 shows an information retention characteristic diagram of an embodiment of the ferroelectric memory cell forming the memory array MARY of FIG. Based on the figure, memory array MAR
The information retention characteristics of the ferroelectric memory cells forming the Y memory array blocks MAB0 to MAB7 and the outline of the operation in each operation mode will be described.

In FIG. 4, the ferroelectric memory cells constituting the memory array blocks MAB0 to MAB7 of the memory array MARY are the electric field applied between the electrodes of the ferroelectric capacitor Cs and the ferroelectric used as the interelectrode material. It has information retention characteristics as shown in the figure in relation to body polarization. That is, the initial ferroelectric substance in the state of point A is brought into that state by applying an electric field + Ep in the positive direction corresponding to the absolute value of the intermediate potential HVC between the electrodes.
To produce maximum polarization in the positive direction + Pp. This polarization gradually decreases as the absolute value of the electric field decreases, but the polarization + Pr remains even at the point C where the electric field becomes zero. On the other hand, the polarization state of the ferroelectric substance is the electric field −E in the opposite direction.
Reversed at the point D to which c is applied, a reverse maximum polarization -Pp is generated at the point E to which the reverse electric field -Ep corresponding to the absolute value of the intermediate potential HVC is applied. This polarization is
Although the absolute value of the electric field gradually decreases, the polarization −Pr remains at the point F where the electric field becomes zero.
Then, it makes a normal rotation at a point G to which a positive electric field + Ec is applied, and reaches the point B.

In this embodiment, complementary bit line B00
The ferroelectric memory cell coupled to the non-inverted signal lines of * to B0n * to B70 * to B7n * is not particularly limited, but the polarization state of the ferroelectric capacitor Cs is + in FIG.
When it is on the negative side, it holds the data of logical "1", and when it is on the negative side, it holds the data of logical "0". Further, the ferroelectric memory cell coupled to the inversion signal line of the complementary bit lines B00 * to B0n * to B70 * to B7n * is logical when the polarization state of the ferroelectric capacitor Cs is on the negative side in FIG. The data of "1" is held, and the data of logic "0" is held when it is on the + side. Each operating point showing the transition of the polarization state of the ferroelectric memory cell will be repeatedly referred to in the description of the specific operation of the ferroelectric nonvolatile RAM or shadow RAM described later.

FIG. 5 shows the ferroelectric nonvolatile RAM of FIG.
The signal waveform diagram of one embodiment of the read operation in the case of adopting the VSS precharge method, that is, in the case of setting the precharge voltage VPC to the ground potential VSS is shown. Specific operations and characteristics of the nonvolatile read operation of the ferroelectric nonvolatile RAM of this embodiment will be described with reference to FIG. In the following signal waveform diagram, the memory array MA
An example is shown in which the read operation is executed by designating the RY word line W0 and the memory array block MAB0 and the sense amplifier block SAB0.

In FIG. 5, the row address strobe signal RASB and the column address strobe signal CASB are used.
Are set to a high level such as the power supply voltage VCC and the ferroelectric nonvolatile RAM is in the non-selected state, the sense amplifier blocks SAB0 to SAB of the sense amplifier SA.
The precharge control signal PC for 7 is the power supply voltage VC
The plate lines VPL0 to VPL7 for the memory array blocks MAB0 to MAB7 of the memory array MARY are both set to a high level such as C and are set to an invalid level such as the ground potential VSS. Also, the common source line CSP0 for the sense amplifier blocks SAB0 to SAB7
.About.CSP7 and CSN0 to CSN7 are set to an invalid level of the ground potential VSS or the power supply voltage VCC, respectively.
The word lines W0 to Wm are all set to a non-selection level such as the ground potential VSS. Needless to say, the precharge voltage VPC is set to the ground potential VSS.

As a result, in the ferroelectric nonvolatile RAM, the memory array block MA of the memory array MARY
Complementary bit lines B00 * to B0 forming B0 to MAB7
n * to B70 * to B7n * are precharged to the precharge voltage VPC, that is, the ground potential VSS by the bit line precharge circuits of the corresponding unit circuits of the sense amplifier blocks SAB0 to SAB7 of the sense amplifier SA. At this time, the memory array blocks MAB0 to MAB
7, each of the ferroelectric memory cells has a polarization state in a range from point B to point C or point E to point F in FIG. 4 and is selectively logic "1" or "0". It is supposed to hold the data of.

In the ferroelectric nonvolatile RAM, the row address strobe signal RASB and the column address strobe signal CASB are set to the low level after a predetermined time while the write enable signal WEB (not shown) is set to the high level. , Selectively starts the non-volatile data read operation. At this time, the address input terminal A0
To Ai are supplied with X address signals AX0 to AXi in a combination designating the word line W0, that is, the row address ra0 in synchronization with the fall of the row address strobe signal RASB, and the column address strobe signal CA.
Y address signals AY0 to AY0 are synchronized with the fall of SB.
AYi is supplied in a combination designating the bit line selection signal YS00, that is, the column address ca0.

In the ferroelectric non-volatile RAM, the precharge control signal PC is set to the low level in response to the fall of the row address strobe signal RASB, and the memory specified by the internal address signals Xi-2 to Xi of the upper 3 bits. Memory array block MAB of array MARY
The plate line VPL0 corresponding to 0 is alternatively at the intermediate potential H
It is an effective level like VC. In addition, the word line W designated by the internal address signals X0 to Xi with a slight delay.
0 is alternatively set to a selection level such as the high voltage VCH,
After a short delay, the common source line CS corresponding to the memory array block MAB0, that is, the sense amplifier block SAB0
P0 and CSN0 are set to an effective level such as the power supply voltage VCC or the ground potential VSS, respectively.

In the ferroelectric non-volatile RAM, the precharge control signal PC is set to the low level, whereby the precharge MOSFET N3 forming the bit line precharge circuit of each unit circuit of the sense amplifier blocks SAB0 to SAB7 of the sense amplifier SA. To N5 are turned off, and the precharge operation for complementary bit lines B00 * to B0n * to B70 * to B7n * of memory array blocks MAB0 to MAB7 is stopped. Also, the plate line VP
In response to the intermediate potential HVC of L0, the plate potential of the ferroelectric capacitor Cs of the ferroelectric memory cell forming the memory array block MAB0 rises, but at this time, the word lines W0 to Wm are set to the non-selection level. Therefore, the polarization state of these ferroelectric memory cells does not change.

When the word line W0 is set to the selection level with a slight delay, in the memory array blocks MAB0 to MAB7 of the memory array MARY, there are a total of 8 × (n + 1) pairs of ferroelectric memory cells coupled to the word line W0. The address selection MOSFETs Qs are turned on all at once. Therefore, in the n + 1 pair of ferroelectric memory cells coupled to the word line W0 of the memory array block MAB0, the complementary bit line B00 * to one electrode of the ferroelectric capacitor Cs is connected.
Since the precharge potential of the B0n * non-inverted and inverted signal lines, that is, the ground potential VSS is transmitted, an electric field in the opposite direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes. As a result, the polarization states of these ferroelectric memory cells are forcibly and simultaneously moved to point E in FIG. At this time, for example, complementary bit lines B00 * to B0n *
In the memory cell coupled to the non-inverted signal line of No. 1 and holding the data of logic "1", a relatively large movement of the negative charge is required due to the polarization reversal from the point B to the point C. The potential of the non-inverted bit line is relatively increased. However, for example, complementary bit lines B00 * to B0n
In the memory cell which is coupled to the non-inverted signal line of * and holds the data of logic "0", the point E not accompanied by the polarization inversion
Since the transition is from point F to point E, the amount of negative charges transferred is small, and the potential rise of the corresponding non-inverted bit line is also small.

Similarly, for example, complementary bit lines B00 * to B
In the memory cell which is coupled to the inversion signal line of 0n * and holds the data of the logic "0", a relatively large movement of the negative charge is required because of the polarization inversion from the point B to the point C. The potential of the corresponding inversion bit line rises relatively large. However, for example, complementary bit lines B00 * to B0
In the memory cell which is coupled to the n * inversion signal line and holds the data of logic "1", the point E which does not involve the polarization inversion
Since the transition is from point F to point E, the amount of negative charges transferred is small and the potential rise of the corresponding inversion bit line is also small.

Incidentally, the corresponding plate lines VPL1 to VP
In the memory array blocks MAB1 to MAB7 in which L7 is kept at an invalid level such as the ground potential VSS, the address selection MOSFETs Qs of a total of 7 × (n + 1) pairs of ferroelectric memory cells coupled to the word line W0 are all at once. Although turned on, the complementary bit lines B10 * to B1n * to B70 * to B7n corresponding to the potentials of the plates of the ferroelectric capacitor Cs, that is, the plate lines VPL1 to VPL7.
The polarization state does not change because it is the same as the precharge potential of the non-inversion and inversion signal lines of *.

The minute potential difference between the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array block MAB0 is caused by the common source lines CSP0 and C0.
When SN0 is set to an effective level such as the power supply voltage VCC or the ground potential VSS, it is amplified by the corresponding unit amplifier circuit of the sense amplifier block SAB0 of the sense amplifier SA to be a binary read signal. These binary read signals are the column address ca.
When the bit line selection signal YS00 corresponding to 0 is set to the high level, the bit line selection signal YS00 is selectively transmitted to the complementary common data line CD *, and is further transmitted from the read amplifier of the main amplifier MA via the output buffer OB and the data output terminal Dout. And is output to the outside of the ferroelectric nonvolatile RAM.

By the way, the sense amplifier block SAB0
The amplifying operation by each unit amplifier circuit is completed, and the complementary bit lines B00 * to B0n * of the memory array block MAB0 are completed.
When a high-level or low-level binary read signal is established on the non-inverted and inverted signal lines of, for example, it is arranged at the intersection of the word line W0 and the non-inverted signal lines of the complementary bit lines B00 * to B0n *, and the logic The high level after amplification of the corresponding non-inverted signal line, that is, the power supply voltage VCC is applied to one electrode of the ferroelectric capacitor Cs of the ferroelectric memory cell holding the data of "1", and the other electrode. That is, the effective level of the plate line VPL0, that is, the intermediate potential HVC is applied to the plate. Therefore, the power supply voltage VCC is provided between the electrodes of these ferroelectric capacitors Cs.
A potential difference between the intermediate potential HVC and the intermediate potential HVC, that is, an electric field in the positive direction corresponding to the absolute value of the intermediate potential HVC is applied, and the polarization state shifts from point E to point B in FIG.

On the other hand, the word line W0 and the complementary bit line B00
One of the electrodes of the ferroelectric capacitor Cs of the ferroelectric memory cell arranged at the intersection with the inversion signal line of * to B0n * and holding the data of logic "1" has the corresponding inversion signal line after amplification. Low level, that is, the ground potential VSS is applied, and the effective level of the plate line VPL0, that is, the intermediate potential HVC is applied to the other electrode. Therefore, between both electrodes of these ferroelectric capacitors Cs,
A potential difference between the intermediate potential HVC and the ground potential VSS, that is, an electric field in the opposite direction corresponding to the absolute value of the intermediate potential HVC is applied, and the polarization state remains at point E in FIG. 4 without transition.

Similarly, the word line W0 and the complementary bit line B0
The corresponding non-inverted signal line is provided on one electrode of the ferroelectric capacitor Cs of the ferroelectric memory cell which is arranged at the intersection with the non-inverted signal line of 0 * to B0n * and holds the data of logic "0". The low level after being amplified, that is, the ground potential VSS is applied, and the effective level of the plate line VPL0, that is, the intermediate potential HVC is applied to the other electrode. Therefore, an electric field in the opposite direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes of these ferroelectric capacitors Cs, and the polarization state thereof is at point E in FIG. 4 without transition.

However, the word line W0 and the complementary bit line B0
The corresponding inversion signal line is amplified at one electrode of the ferroelectric capacitor Cs of the ferroelectric memory cell which is arranged at the intersection with the inversion signal line of 0 * to B0n * and holds the data of logic "0". The subsequent high level, that is, the power supply voltage VCC is applied, and the intermediate potential HVC of the plate line VPL0 is applied to the other electrode, that is, the plate. Therefore, an electric field in the positive direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes of these ferroelectric capacitors Cs, and the polarization state thereof shifts from point E to point B in FIG. .

That is, the ferroelectric nonvolatile R of this embodiment
In AM, the effective level of the plate line VPL0 is set to the intermediate potential HVC, so that the sense amplifier block S
Immediately after the amplification operation of the minute read signal by each unit amplifying circuit of AB0 is completed and the binary read signal is established on the complementary bit lines B00 * to B0n *, immediately after n + 1 strong signals are coupled to the selected word line W0. This means that the non-volatile data rewriting operation to the dielectric memory cell is started, and these rewriting operations are completed while the designated 1-bit read data is output through the data output terminal Dout. , There is no waiting for rewriting. As a result, only the designated word line W0 is brought into the selected state, in other words, the designated word line W0 is selected.
Since the non-volatile data can be rewritten to the selected ferroelectric memory cell without setting the plate line VPL0 to the valid level or the invalid level while 0 is in the selected state, the cycle of the ferroelectric nonvolatile RAM can be realized. It is possible to speed up the time and speed up the machine cycle of the system including this.

As described above, the memory array MAR
The memory array blocks MAB0 to MAB7 of Y are selectively activated by setting the corresponding plate lines VPL0 to VPL7 to an effective level such as the intermediate potential HVC, and the sense amplifiers of the sense amplifier SA. The blocks SAB0 to SAB7 are corresponding common source lines CSP.
0 to CSP7 and CSN0 to CSN7 are activated by being set to an effective level such as the power supply voltage VCC or the ground potential VSS, respectively. As a result, the word lines W0 to Wm are connected to the memory array blocks MAB0 to MAB.
Although shared by AB7, the required operating current at the time of the read operation in the nonvolatile mode of the ferroelectric nonvolatile RAM can be reduced, the cost can be reduced, and the sense amplifier can be operated. It is supposed that the power supply noise accompanying this can be suppressed and the read operation can be stabilized.

FIG. 6 shows the ferroelectric nonvolatile RAM of FIG.
VCC precharge method, that is, precharge voltage VP
A signal waveform diagram of one embodiment during a read operation when C is the power supply voltage VCC is shown. Since this embodiment basically follows the embodiment of FIG. 5, only the parts different from this will be described.

In FIG. 6, when the ferroelectric non-volatile RAM is in the non-selected state, the plate lines VPL0 to VPL7 for the memory array blocks MAB0 to MAB7 of the memory array MARY are both set to an invalid level like the power supply voltage VCC. The precharge voltage VPC is also set to the power supply voltage VCC. The non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * to B70 * to B7n * forming the memory array blocks MAB0 to MAB7 of the memory array MARY receive the high level of the precharge control signal PC and receive the power supply voltage VCC. Is precharged to

When the ferroelectric non-volatile RAM is selected in the read mode, the ferroelectric non-volatile RAM
In response to the fall of the row address strobe signal RASB, the plate line VPL0 designated by the internal address signals Xi-2 to Xi of the upper 3 bits is alternatively set to the effective level such as the intermediate potential HVC. Therefore, at the time when the word line W0 is alternatively set to the selection level, n + coupled to the word line W0 of the memory array block MAB0.
The precharge potential of the complementary bit lines B00 * to B0n *, that is, the precharge potential of the complementary bit lines B00 * to B0n *, that is, the power supply voltage VC is provided on one electrode of the ferroelectric capacitors Cs of the pair of ferroelectric memory cells.
C is transmitted. Therefore, an electric field in the positive direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes, and the polarization states of these ferroelectric memory cells are forcibly and simultaneously moved to point B in FIG. To do. At this time, for example, in the memory cell which is coupled to the non-inverted signal lines of the complementary bit lines B00 * to B0n * and holds the data of logic "0", the polarization inversion from the points E to F to the point B is involved. A relatively large amount of positive charge transfer is required, and the potential of the corresponding non-inverted signal line drops relatively large. However, for example, in the memory cell which is coupled to the non-inverted signal lines of the complementary bit lines B00 * to B0n * and holds the data of logic "1", the transition from the point B to the point B without the polarization inversion can be achieved. Therefore, the amount of movement of positive charges is small and the potential drop of the corresponding non-inverted bit line is also small.

Similarly, for example, complementary bit lines B00 * to B
In the memory cell which is coupled to the inversion signal line of 0n * and holds the data of the logic "1", a relatively large movement of the positive charge is required in order to accompany the polarization reversal from the point E to the point F, The potential of the corresponding inversion bit line rises relatively large. However, for example, complementary bit lines B00 * to B0
In the memory cell which is coupled to the n * inversion signal line and holds the data of logic "0", the point B which does not involve the polarization inversion.
Since the transition is from point C to point B, the amount of positive charge transfer is small and the potential rise of the corresponding inversion bit line is also small.

Incidentally, the corresponding plate lines VPL1 to VP
In the memory array blocks MAB1 to MAB7 in which L7 is kept at an invalid level such as the power supply voltage VCC, the address selection MOSFETs Qs of a total of 7 × (n + 1) pairs of ferroelectric memory cells coupled to the word line W0 are all at once. Although turned on, the complementary bit lines B10 * to B1n * to B70 * to B7n corresponding to the potentials of the plates of the ferroelectric capacitor Cs, that is, the plate lines VPL1 to VPL7.
Since the power source voltage VCC is the same as the precharge potential of the non-inverted and inverted signal lines, the polarization state does not change.

The amplification operation by each unit amplifier circuit of the sense amplifier block SAB0 ends, and a high level or low level binary read signal is applied to the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array block MAB0. When established, the ferroelectric capacitor Cs of the ferroelectric memory cell arranged at the intersection of the word line W0 and the non-inverted signal line of the complementary bit lines B00 * to B0n * and holding the data of logic "1". One of the electrodes has a high level after amplification of the corresponding non-inverted signal line, that is, the power supply voltage VC.
C is applied, and the intermediate potential HVC of the plate line VPL0 is applied to the other electrode, that is, the plate. Therefore, between the electrodes of these ferroelectric capacitors Cs,
A positive electric field corresponding to the absolute value of the intermediate potential HVC is applied, and its polarization state remains at point B in FIG. 4 without transition.

On the other hand, the word line W0 and the complementary bit line B00
One of the electrodes of the ferroelectric capacitor Cs of the ferroelectric memory cell arranged at the intersection with the inversion signal line of * to B0n * and holding the data of logic "1" has the corresponding inversion signal line after amplification. Is applied at the low level, that is, the ground potential VSS, and the intermediate potential HVC of the plate line VPL0 is applied to the other electrode. Therefore, an electric field in the opposite direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes of these ferroelectric capacitors Cs, and the polarization state thereof shifts from point B to point E in FIG. .

Similarly, the word line W0 and the complementary bit line B0
The corresponding non-inverted signal line is provided on one electrode of the ferroelectric capacitor Cs of the ferroelectric memory cell which is arranged at the intersection with the non-inverted signal line of 0 * to B0n * and holds the data of logic "0". The low level after being amplified, that is, the ground potential VSS is applied, and the effective level of the plate line VPL0, that is, the intermediate potential HVC is applied to the other electrode. Therefore, an electric field in the opposite direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes of these ferroelectric capacitors Cs, and the polarization state thereof shifts from point B to point E in FIG. . However, the word line W0 and the complementary bit lines B00 * to B
It is arranged at the intersection with the 0n * inverted signal line and has a logic "0".
Is applied to one electrode of the ferroelectric capacitor Cs of the ferroelectric memory cell that holds the data of No. 3, the high level after the amplification of the corresponding inversion signal line, that is, the power supply voltage VCC, and to the other electrode, that is, the plate. , Plate line VPL0
Intermediate potential HVC is applied. Therefore, an electric field in the positive direction corresponding to the absolute value of the intermediate potential HVC is applied between the electrodes of these ferroelectric capacitors Cs, and the polarization state remains at point B in FIG. 4 without transition.

That is, the ferroelectric nonvolatile R of this embodiment
In AM, the effective level of the plate line VPL0 is set to the intermediate potential HVC, so that the sense amplifier block S
Immediately after the amplification operation of the minute read signal by each unit amplifier circuit of AB0 is completed and the binary read signal is established on the complementary bit lines B00 * to B0n * of the memory array block MAB0, the word line W0 is coupled to the selected word line W0. N +
This means that the rewriting operation of the non-volatile data to one ferroelectric memory cell is started, and by this, the same effect as in FIG. 5 can be obtained.

FIG. 7 shows the ferroelectric nonvolatile RAM of FIG.
6 is a signal waveform diagram of an example during the distributed read operation of FIG. Since this embodiment basically follows the embodiment of FIG. 5, the description will be added only to the parts different from this. Further, in FIG. 7, portions related to the memory array blocks MAB2 to MAB6 and the sense amplifier blocks SAB2 to SAB6 are omitted.

In FIG. 7, when the ferroelectric nonvolatile RAM is selected in the read mode, the designated word line W0 is set to the selection level like the high voltage VCH prior to the plate lines VPL0 to VPL7. It Further, the plate lines VPL0 to VPL7 are sequentially set to an effective level such as the intermediate potential HVC after a predetermined time, and when a predetermined time elapses after these plate lines VPL0 to VPL7 are set to the effective level, Corresponding common source lines CSP0 to CSP7 and CSN0 to CSN7 are sequentially set to the effective levels of the power supply voltage VCC and the ground potential VSS.

In the ferroelectric non-volatile RAM, the plate lines VPL0 to VPL7 are sequentially set to the effective level, and corresponding memory array blocks MAB0 to MAB7 are received.
Complementary bit line B00 to which the minute read signals of the n + 1 ferroelectric memory cells coupled to the word line W0 of
It is sequentially output to * to B0n * to B70 * to B7n *. Further, these minute read signals are transmitted to the corresponding common source lines CSP0 to CSP7 and CSN0 to CS.
When N7 is sequentially set to the effective level, it is amplified by the corresponding n + 1 unit amplifier circuits of the sense amplifier blocks SAB0 to SAB7, and becomes a binary read signal.

That is, the ferroelectric nonvolatile R of this embodiment
In the AM, the plate lines VPL0 to VPL7 are sequentially set to the effective level after a predetermined time, so that the eight memory array blocks MAB0 to MAB7 are sequentially activated, and the common source lines CSP0 to CSP7 and CSN0. ~ CSN7 are sequentially set to the effective level after a predetermined time, so that eight sense amplifier blocks S
AB0 to SAB7 are memory array blocks MAB0 to M
The active states are sequentially set in correspondence with AB7. As a result, the power noise due to all 8 × (m + 1) × (n + 1) unit amplifier circuits of all the sense amplifier blocks SAB0 to SAB7 being operated simultaneously is dispersed and suppressed, and the ferroelectricity is improved. The read operation of the body nonvolatile RAM can be stabilized. Needless to say, the operation of this embodiment is effective for continuous read operation such as serial memory.

FIG. 8 shows a signal waveform diagram of an embodiment of the distributed recall operation of the shadow RAM to which the present invention is applied. Since this embodiment basically follows the embodiment of FIG. 7, the description will be added to the parts different from this. Further, in FIG. 8, portions related to the memory array blocks MAB2 to MAB7 and the sense amplifier blocks SAB2 to SAB7 are omitted.

In FIG. 8, the shadow RA of this embodiment is
M has a recall mode designated by a mode control signal (not shown) and a column address strobe signal CA.
The so-called CBR (CAS Before R) in which SB is set to the low level prior to the row address strobe signal RASB
By executing the AS) cycle, a recall operation for shifting from the nonvolatile mode to the volatile mode is started.
In the shadow RAM, the row address strobe signal RA
The precharge control signal PC is set to the low level in response to the low level of SB, and the final word line Wm designated with a slight delay is alternatively set to the selection level such as the high voltage VCH. In addition, the plate lines VPL0 to VPL7 are sequentially set to an effective level like the intermediate potential HVC after a predetermined time, and when the predetermined time elapses, the corresponding common source lines CSP0 to CSP7 and CSN0.
~ CSN7 is sequentially set to the valid level.

In the shadow RAM, the plate line VPL0
.. to VPL7 are sequentially set to the effective level, complementary bit lines B00 * corresponding to the minute read signals of the n + 1 ferroelectric memory cells coupled to the word lines W0 of the corresponding memory array blocks MAB0 to MAB7. ~ B0
It is sequentially output to n * to B70 * to B7n *. In addition, these minute read signals are common source line CS
By sequentially setting P0 to CSP7 and CSN0 to CSN7 to valid levels, the sense amplifier block SAB0
To ferroelectric memory cells of n + 1 ferroelectric memory cells coupled to the word lines W0 of the memory array blocks MAB0 to MAB7 after being amplified by the corresponding n + 1 unit amplifier circuits of the SAB7 to be binary read signals. The accumulated charge is written in the inter-electrode capacitance of the body capacitor Cs. Precharge voltage VPC is changed to intermediate potential HVC while precharge control signal PC is at low level, and all complementary bit lines B00 * to B0n * to B7 forming memory array blocks MAB0 to MAB7.
The non-inverted and inverted signal lines of 0 * to B7n * are precharged to the intermediate potential HVC when the precharge control signal PC is returned to the high level. As a result, the memory array blocks MAB0 to MAB of the memory array MARY
The data of all the ferroelectric memory cells constituting 7 become so-called volatile data, and the shadow RAM shifts to the volatile mode.

That is, in the shadow RAM of this embodiment, the eight memory array blocks MAB0 to MAB7 are sequentially activated by setting the plate lines VPL0 to VPL7 to a valid level sequentially after a predetermined time. Together with common source lines CSP0 to CSP7 and C
By sequentially setting SN0 to CSN7 to valid levels after a predetermined time, the eight sense amplifier blocks SAB0
To SAB7 are memory array blocks MAB0 to MAB7
In the same manner as the ferroelectric non-volatile RAM of the embodiment shown in FIG. 7, a total of 8 sense amplifier blocks SAB0 to SAB7 × (m +).
1) × (n + 1) unit amplifying circuits can be dispersed and suppressed due to power supply noise caused by simultaneous operation of the unit amplifying circuits, and the shadow RAM read operation can be stabilized.

The operational effects obtained from the above embodiments are as follows. (1) Ferroelectric non-volatile RAM adopting plate selection method
In a ferroelectric memory such as a shadow RAM, a plate line is set to a valid level before the selection operation of a designated word line is started, and an invalid level is set after the word line is deselected. The effective level of the plate line is an intermediate potential between the high level and the low level after amplification of the binary read signal on the bit line, that is, the power supply voltage and the ground potential, and the invalid level thereof is the power supply voltage which is the precharge potential of the bit line. Alternatively, by setting it to the ground potential, only the designated word line is brought into the selected state, in other words, the plate line is not brought to the valid level or the invalid level while the designated word line is brought into the selected state, The effect that the rewriting of the non-volatile data to the selected ferroelectric memory cell can be realized is obtained. (2) According to the above item (1), the cycle time of the ferroelectric nonvolatile RAM and the shadow RAM adopting the plate selection method can be shortened, and the machine cycle of the system including this can be shortened. To be

(3) In the above items (1) and (2),
A memory array such as a ferroelectric non-volatile RAM and a shadow RAM is divided into a plurality of memory array blocks in units of, for example, a predetermined number of bit lines, and a corresponding plate line is set to an effective level to selectively activate it. In addition, by dividing the sense amplifier into a plurality of sense amplifier blocks corresponding to the memory array blocks and selectively activating them together with the corresponding memory array blocks, the sense amplifier corresponding to the specified memory array block It is possible to obtain an effect that only a block is selectively activated to reduce a required operation current during a read operation in a nonvolatile mode such as a ferroelectric nonvolatile RAM and a shadow RAM. (4) According to the above item (3), it is possible to suppress the power supply noise of the ferroelectric nonvolatile RAM and the shadow RAM having a large capacity, to stabilize the read operation, and to reduce the power consumption thereof. The effect of being able to be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1 and FIG. 2, the memory array block MA
B0 to MAB7 and sense amplifier block SAB0
~ Bits of the internal address signal for selectively activating SAB7 can be set arbitrarily. In addition, the ferroelectric non-volatile RAM can adopt the shared sense method, and the memory array MARY and the sense amplifier S can be used.
The number of divisions of A can also be set arbitrarily. The ferroelectric non-volatile RAM can take any bit configuration such as × 4 bits, × 8 bits or × 16 bits,
The block configuration, the names, combinations and effective levels of the activation control signal and the internal control signal, the polarity of the power supply voltage, and the like can adopt various embodiments.

In FIG. 3, the memory array MARY of the ferroelectric nonvolatile RAM, that is, the memory array block MA.
B0 to MAB7 can include a predetermined number of redundant elements. Further, the ferroelectric nonvolatile RAM may have a so-called one-cell / one-transistor array configuration, as shown in FIG. 9, for example, or may have various other array configurations. Various embodiments can be adopted for the specific configurations of the memory array MARY and the sense amplifier SA, the conductivity type of the MOSFET, and the like.

In FIG. 4, the information holding characteristic of the ferroelectric memory cell is a standard example and does not limit the present invention. 5 to 8, the plate line VPL0
The effective level of VPL7 is at the intermediate potential HVC, provided that it is between the power supply voltage VCC and the ground potential VSS.
Can be set to any potential other than. Further, the precharge control signal PC is the sense amplifier blocks SAB0 to SAB.
It may be provided for every 7 and alternatively set to the low level corresponding to the sense amplifier block. The starting control signal, the internal control signal, and the absolute time relationship and effective level of the internal signal of the ferroelectric nonvolatile RAM and the shadow RAM are not limited to those in this embodiment.

In the above description, the invention made by the present inventor was mainly applied to the ferroelectric non-volatile RAM and the shadow RAM, which are the fields of application in the background, but the invention is not limited thereto. Without
For example, the present invention can be applied to a digital integrated circuit device such as a ferroelectric ROM (read only memory) that performs only a read operation in a non-volatile mode, a ferroelectric non-volatile RAM, and a single-chip microcomputer that incorporates a ferroelectric ROM. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a ferroelectric memory having a memory array in which at least ferroelectric memory cells are arranged in a lattice, and an apparatus or system including the ferroelectric memory.

[0086]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a ferroelectric memory such as a ferroelectric non-volatile RAM and a shadow RAM adopting the plate selection method, the plate line is set to an effective level before the selection operation of the designated word line is started, and this word line is After being deselected, it becomes an invalid level,
The effective level of the plate line is set to an intermediate potential between the high level and the low level after amplification of the binary read signal on the bit line, that is, the power supply voltage and the ground potential, and the invalid level is set to the power supply voltage or the precharge potential of the bit line. Set to ground potential. Further, a memory array such as a ferroelectric nonvolatile RAM and a shadow RAM is divided into a plurality of memory array blocks in units of, for example, a predetermined number of bit lines,
These memory array blocks are selectively activated by selectively setting the corresponding plate line to a valid level, and the sense amplifier is divided into a plurality of sense amplifier blocks corresponding to the memory array blocks. It is selectively activated together with the corresponding memory array block. As a result, only the selected word line is brought into the selected state, in other words, the selected ferroelectric line is not brought to the valid level or the invalid level while the designated word line is in the selected state. It is possible to rewrite non-volatile data to the body memory cell,
Only the sense amplifier block corresponding to the designated memory array block is selectively activated to reduce the required operation current during the nonvolatile read operation of the ferroelectric nonvolatile RAM and the shadow RAM. As a result, the cycle time of the ferroelectric non-volatile RAM and shadow RAM adopting the plate selection method can be shortened, the machine cycle of the system including the same can be shortened, and the capacity of the ferroelectric non-volatile RAM can be increased. Sex RAM
Also, power supply noise of the shadow RAM and the like can be suppressed to stabilize the read operation, and at the same time, lower power consumption can be achieved.

[Brief description of drawings]

FIG. 1 is a ferroelectric nonvolatile RAM to which the present invention is applied.
FIG. 3 is a block diagram showing one embodiment of the present invention.

2 is a block diagram showing an embodiment of a memory array and a sense amplifier included in the ferroelectric nonvolatile RAM of FIG.

3 is a partial circuit diagram showing an embodiment of a memory array and a sense amplifier included in the ferroelectric nonvolatile RAM of FIG.

FIG. 4 is an information retention characteristic diagram showing an example of a ferroelectric memory cell forming the memory array of FIG.

5 is a signal waveform diagram showing an embodiment during a read operation in which the precharge voltage of the ferroelectric nonvolatile RAM of FIG. 1 is set to the ground potential.

FIG. 6 is a signal waveform diagram showing an embodiment at the time of a read operation in which the precharge voltage of the ferroelectric nonvolatile RAM of FIG. 1 is used as a power supply voltage.

FIG. 7 is a signal waveform diagram showing one embodiment during a distributed read operation in which the precharge voltage of the ferroelectric nonvolatile RAM of FIG. 1 is set to the ground potential.

FIG. 8 is a signal waveform diagram showing one embodiment during a distributed recall operation in which the precharge voltage of the shadow RAM to which the present invention is applied is the ground potential.

FIG. 9 is a ferroelectric nonvolatile RAM to which the present invention is applied.
6 is a partial circuit diagram showing another embodiment of the memory array and the sense amplifier included in FIG.

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XL ... X address latch, AB ... address buffer, SA ... sense amplifier, YD ... Y address decoder, YL ... Y address latch, MA ... main Amplifier, IB ... input buffer, OB ... output buffer, C
G: Clock generation circuit. Din …… Data input terminal,
Dout ... Data output terminal, RASB ... Row address strobe signal input terminal, CASB ... Column address strobe signal input terminal, WEB ... Write enable signal input terminal, OEB ... Output enable signal input terminal, A0-Ai. Address input terminal. MAB0-MA
B7 ... Memory array block, W0-Wm ... Word line, VPL0-VPL7 ... Plate line, SAB0-S
AB7 ... Sense amplifier block, CD * ... Complementary common data line, PC ... Precharge control signal, VPC ...
Precharge voltage, CSP0-CSP7, CSN0-C
SN7 ... Common source line, YS00 to YS0n to YS70 to YS7n ... Bit line selection signal. B00 * ~
B0n * to B70 * to B7n * ... Complementary bit lines,
Cs ... Ferroelectric capacitor, Qs ... Address selection M
OSFET, P1 to P2 ... P-channel MOSFE
T, N1 to N7 ... N-channel MOSFET. DW0
DW1 ... Dummy word line, Cy ... Dummy cell ferroelectric capacitor, Qy ... Dummy cell address selection MOSFET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Nagashima 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Masatoshi Hasegawa 2326 Imai, Ome City, Tokyo Hitachi Device Development Center, Ltd. (72) Inventor Seiji Narui 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Yasunobu Aoki 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Cho-S. I Engineering Co., Ltd.

Claims (7)

[Claims] 1. A word line and a bit line which are arranged orthogonally to each other, a ferroelectric memory cell which is arranged in a substantially lattice shape at an intersection of the word line and the bit line, and a predetermined number of rows or columns. The plates of the ferroelectric memory cells are commonly coupled to each other and set to an effective level to selectively select the corresponding ferroelectric memory cells arranged in the predetermined number of rows or columns. And a minute read signal output to the corresponding bit line from the ferroelectric memory cell provided corresponding to the bit line of the memory array and placed in a selected state. And a sense amplifier including a unit amplifier circuit that amplifies the signal to two levels to obtain a binary read signal, and sets the effective level of the plate line to a predetermined potential between the first and second levels. A ferroelectric memory characterized by the above. 2. The effective level of the plate line is an intermediate potential between the first and second levels, and the invalid level thereof is the first or second level. The plate line is set to the valid level before the selection operation of the designated word line is started, and is set to the invalid level after the word line is deselected. A ferroelectric memory according to item 1. 3. A memory array including a plurality of memory array blocks each including a predetermined number of bit lines and sharing a word line and being selectively activated, and a memory array provided corresponding to the memory array block. And a sense amplifier including a plurality of sense amplifier blocks that are selectively activated, together with the memory array block described above. 4. The memory array block and the sense amplifier block are activated one after another alternatively or after a predetermined time according to a predetermined address signal. Dielectric memory. 5. The bit line is precharged to the first or second level, and a plate of a ferroelectric capacitor of a ferroelectric memory cell forming each of the memory array blocks comprises: The sources of the amplification MOSFETs of the unit amplifier circuits that are commonly coupled to the corresponding plate lines and that configure each of the sense amplifier blocks are commonly coupled to the corresponding common source lines. Each of them is selectively activated by setting the corresponding plate line to the intermediate potential of the first or second level, and each of the sense amplifier blocks is connected to the corresponding common source line by operating power. Is selectively activated by being supplied. Ferroelectric memory. 6. The ferroelectric memory is a ferroelectric non-volatile RAM, and the memory array block and the sense amplifier block are selectively activated when the ferroelectric non-volatile RAM is in a read mode. 7. The ferroelectric memory according to claim 3, wherein the ferroelectric memory is in a state. 7. The ferroelectric memory is a shadow RAM
5. The memory array block and the sense amplifier block are selectively activated when the shadow RAM is in a recall mode. 5. Ferroelectric memory.