JPH11265572A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Problem] A dynamic R using a boost sense method
Higher speed and lower power consumption of AM and the like. SOLUTION: Complementary input / output nodes S0 * to Sn * of each unit amplifier circuit of a sense amplifier SA and a boost control signal BS
A boost sensing method including boost capacitances C1 and C2 provided between the shared MOSFET N
3 and N4 and a dynamic RAM or the like employing a shared sense method including NC and ND, a drive MOSFET P1 for overdrive is provided between a power supply voltage VCC and a common source line CSP, and a boost capacitance C
1 and C2, the complementary input / output node S0 of the unit amplifier circuit
* After the boost of Sn *, the shared MOSFET N
The drive MOSFET P1 is turned on while all the switches 3 and N4 and the NC and ND are turned off, and each unit amplifier circuit is overdriven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (random access memory) employing a boost sense system and a technique particularly effective when used for speeding up and reducing power consumption. is there.

[0002]

2. Description of the Related Art A memory array including word lines and complementary bit lines arranged orthogonally, dynamic memory cells arranged in a lattice at the intersections of these word lines and complementary bit lines, and each complementary bit line of the memory array There is a semiconductor memory device such as a dynamic RAM including a sense amplifier including a unit amplifier circuit provided corresponding to the above. In such a dynamic RAM or the like, a pair of boost capacitors are provided between the non-inverting and inverting input / output nodes of each unit amplifier circuit constituting the sense amplifier and the boost control signal line, and the selected word line of the memory array is provided. After the minute read signal of the memory cell coupled to the corresponding complementary bit line is output, the potential of the non-inverting and inverting input / output nodes of each unit amplifier circuit is raised to reduce the voltage of the dynamic RAM or the like. So-called boost sense method (CABS method:
Charge Amplifying-Boosted
Sensing Scheme) is, for example, 199
In May 1995, IEE Journal of Solid State Circuits (JO)
URNAL OF SOLID-STATE CIRC
UITS), VOL. 32, no. 5, pages 642 to 648.

On the other hand, each unit amplifier circuit constituting a sense amplifier such as a dynamic RAM is selectively supplied with a predetermined high potential side and low potential side operation power supply to a pair of common source lines. And simultaneously amplify the small read signals output from the memory cells coupled to the selected word line of the memory array via the corresponding complementary bit lines, and raise the high-potential-side operation power supply to a high level. And a binary read signal that sets the low-potential-side operation power supply to a low level.

In recent years, as the technology for miniaturization and higher integration of semiconductor integrated circuits has advanced and the operating power supply voltage for dynamic RAMs and the like has been reduced, the amplitude of the binary read signal obtained by the amplifying operation of the unit amplifier circuit has increased. The drain-source voltage of a MOSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a generic name of an insulated gate type field effect transistor) that is compressed and constitutes a unit amplifier circuit is reduced. However, the amplification operation tends to be slow, and the read operation of a dynamic RAM or the like tends to be slow. To cope with this, the potential of the common source line corresponding to the high-potential-side operation power supply is temporarily increased from the final high level after amplification at the non-inverting and inverting input / output nodes of each unit amplifier circuit. The so-called overdrive sense system, which can speed up the amplification operation by temporarily increasing the drain-source voltage of the MOSFET constituting the unit amplification circuit and speed up the read operation of a dynamic RAM or the like, is becoming common. is there.

[0005]

Prior to the present invention, the present inventors proceeded with the development of a dynamic RAM employing the above boost sense system, and noticed the following problems in the course of the development. That is, this dynamic RAM
As shown in FIG. 4, each unit circuit of the sense amplifier SA is provided with a unit amplifier circuit composed of P-channel MOSFETs P2 and P3 and N-channel MOSFETs N8 and N9. Nodes S0T to SnT (here, a so-called non-inverted signal or the like which is selectively set to a high level when it is made valid is denoted by adding a T to the end of its name. The same applies hereinafter) and inverted inputs and outputs. Nodes S0B to Sn
Between B (here, a so-called inverted signal or the like which is selectively set to a low level when the signal is made valid is denoted by suffixed with B. The same applies hereinafter) and the boost control signal line BST. Has a pair of boost capacitors C3 and C4
Is provided.

The boost control signal line BST to which the drain-source electrodes of the boost capacitors C3 and C4 constituting each unit circuit of the sense amplifier SA are coupled has the same level as the normal ground potential VSS as illustrated in FIG. And the selected word line WL of the memory array ARYL, for example.
The complementary bit line BL0 * to which the minute read signal corresponding to the data held in the (n + 1) memory cells coupled to 0 corresponds
To BLn * (here, for example, the non-inverted bit line BL0T and the inverted bit line BL0B
It is represented by adding * like 0 *. The same applies hereinafter), that is, the complementary input / output node S0 of each unit amplifier circuit of the sense amplifier SA.
* To Sn *, and the complementary input / output nodes and the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR on both sides.
And shared MOSFETs N3 and N4 provided between
Also, when NC and ND are all turned off, they are set to a high level like power supply voltage VCC. The boost capacitors C3 and C4 are connected to the boost control signal BST.
Rises to the high level, the potentials of the non-inverting input / output nodes S0T to SnT and the inverting input / output nodes S0B to SnB of each unit amplifier circuit are simultaneously raised, and the level difference is slightly enlarged.

As a result, when attention is paid to the N-channel MOSFETs N8 and N9 constituting the unit amplifier circuit, the voltage between the drain and the source is increased and the amplification operation is accelerated. However, when viewed from the P-channel MOSFETs P2 and P3, Conversely, it has been found that the drain-source voltage becomes small and the amplification operation becomes slow, and the reading operation of the dynamic RAM is not accelerated as expected.

On the other hand, in a conventional dynamic RAM employing an overdrive sense system, for example, a shared MOS on the memory array ARYL including a selected word line WL0 is used.
With the FETs N3 and N4 kept on, that is, with the complementary bit lines BL0 * to BLn * of the memory array ARYL connected to the complementary input / output nodes S0 * to Sn * of each unit amplifier circuit of the sense amplifier SA, The operation of amplifying the minute read signal by each unit amplifier circuit is performed. The final high level of each unit amplifier circuit after amplification at the non-inverting and inverting input / output nodes is the internal voltage VDL generated by lowering the power supply voltage VCC, and its low level is the ground potential VSS. However, the common source line CSP that supplies the high-potential-side operation power supply of the unit amplifier circuit has a complementary input / output node of each unit amplifier circuit, that is, a complementary bit line B.
For a predetermined period during which the high level of the non-inverted and inverted signal lines of L0 * to BLn * does not become higher than necessary,
A power supply voltage VCC having a higher potential than the internal voltage VDL is supplied.

As is well known, complementary bit lines BL0 * -BLn * and B of memory arrays ARYL and ARYR are
A relatively large parasitic capacitance is coupled to R0 * to BRn *, and the period during which the common source line CSP is overdriven to the power supply voltage VCC also varies due to process variations. As a result, the power consumption of the sense amplifier at the time of overdrive increases, and the dynamic RAM
In addition, the reduction in power consumption is hindered, and the so-called excessive overdrive when the overdrive period becomes too long makes it difficult to invert and rewrite the stored data, or the time required for the inversion and rewrite of the stored data becomes long.

An object of the present invention is to increase the speed and lower the power consumption of a dynamic RAM or the like employing a boost sense system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like that employs a boost sense method and a shared sense method, after the non-inverting of the unit amplifier circuit and the inverting input / output node have been boosted by the boost capacitance, the shared MOSF
The unit amplifier circuit is overdriven while all the ETs are in the off state.

According to the above-described means, N units constituting each unit amplifier circuit of the sense amplifier by the boost sense operation are provided.
The drain-source voltage of the channel MOSFET is increased and the P-channel M
By increasing the drain-source voltage of the OSFET to speed up the amplification operation of the unit amplifier circuit, a dynamic RA
It is possible to speed up the read operation of M or the like. Also,
At the time of overdrive operation, the corresponding complementary bit line of the memory array is disconnected from the complementary input / output node of each unit amplifier circuit, the load is reduced, and the dynamic RAM
And low power consumption, and shared MOSFE
At the time point when T is returned to the ON state, the potential of the non-inverted or inverted input / output node of the overdriven unit amplifier circuit is reduced by charge sharing with the parasitic capacitance of the corresponding complementary bit line of the memory array, and Inversion rewriting can be performed reliably and at high speed.

[0014]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment includes, but is not limited to, eight memory mats MAT0 to MAT7. Dynamic type R
AM adopts a shared sense system and uses a memory mat MAT.
0 to MAT7, as represented by the memory mat MAT0, a pair of memory arrays ARYL and ARYR sandwiching the sense amplifier SA, and a pair of X address decoders XDL provided corresponding to each memory array.
And XDR. Memory mats MAT0-MAT
7 further includes a Y address decoder YD provided commonly to both memory arrays, a write amplifier WA and a main amplifier MA.

The memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 each have a predetermined number of word lines arranged in parallel in the vertical direction and a predetermined number of complementary bit lines arranged in parallel in the horizontal direction. And respectively.
At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.
The specific configuration of the memory arrays ARYL and ARYR will be described later in detail.

The word lines forming the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are coupled to corresponding X address decoders XDL or XDR below them, and each of them is alternatively selected. To the X address decoders XDL and XDR of the memory mats MAT0 to MAT7, the i + 1-bit internal address signals X0 to Xi are commonly supplied from the X address buffer XB, and the internal control signal XG (not shown) is commonly supplied from the timing generation circuit TG. Supplied to Also,
The X address buffer XB receives an X address signal A from an external access device through address input terminals A0 to Ai.
X0 to AXi are supplied in a time-division manner, and an internal control signal XL is supplied from the timing generation circuit TG.

The X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are taken in according to the internal control signal XL, held, and based on these X address signals, internal address signals X0 to Xi are formed to generate a memory mat MAT.
0 to MAT7 to the X address decoders XDL and XDR. At this time, the memory mats MAT0 to MAT7
The X address decoders XDL and XDR selectively operate when the internal control signal XG is set to the high level and the internal address signal Xi of the most significant bit is set to the low level or the high level, for example. Address signals X0 to X supplied from
i to decode the memory array ARYL or ARYR
Is alternatively set to a predetermined selection level.

Next, the complementary bit lines constituting the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are respectively connected to corresponding unit circuits of the sense amplifier SA inside. The sense amplifier SA is supplied with n + 1-bit bit line selection signals YS0 to YSn (not shown) from the Y address decoder YD, and shared control signals SHL and SHR, a precharge control signal PC, and a sense amplifier drive signal PA1 from a timing generation circuit TG. , PA2B, PA3 and a boost control signal BST. Also, a Y address decoder YD
Are supplied with i + 1-bit internal address signals Y0 to Yi from a Y address buffer YB, and an internal control signal YG (not shown) from a timing generation circuit TG. The Y address buffer YB is supplied with i + 1-bit Y address signals AY0 to AYi from an external access device via address input terminals A0 to Ai in a time-division manner, and is supplied with an internal control signal YL from a timing generation circuit TG. You.

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi in accordance with the internal control signal YL and hold the same, and form the internal address signals Y0 to Yi based on these Y address signals to obtain the memory mat MAT.
0 to MAT7 to the Y address decoder YD. At this time, the Y address decoders YD of the memory mats MAT0 to MAT7 are selectively activated by receiving the high level of the internal control signal YG, and the internal address signals Y0 to Y
i, and the corresponding bits of the bit line selection signals YS0 to YSn for the sense amplifier SA are alternatively set to the high level.

Each of the sense amplifiers SA of the memory mats MAT0 to MAT7 includes a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of the memory arrays ARYL and ARYR. Each of these unit circuits is a pair of CMOs.
A unit amplifier circuit in which S (complementary MOS) inverters are cross-coupled, and three N-channel precharges M
A bit line precharge circuit in which OSFETs are connected in series and parallel, and a pair of N-channel type switch MOSFETs
T. On the left side, each unit circuit of the sense amplifier, that is, the complementary input / output node of each unit amplifier circuit, is connected to the corresponding complementary bit line of the memory array ARYL via an N-channel type shared MOSFET that receives the shared control signal SHL in common. Coupled, and on the right side, are coupled to the corresponding complementary bit lines of the memory array ARYR via other shared MOSFETs commonly receiving the shared control signal SHR.

The shared control signals SHL and SHR
As described later, when the dynamic RAM is set to the non-selected state, it is set to a predetermined high level. When the dynamic RAM is set to the selected state, one of them is set according to, for example, the internal address signal Xi of the most significant bit. One of them is selectively set to a predetermined low level. Thereby, the complementary input / output node of each unit circuit of the sense amplifier SA is connected to the non-selected state of the dynamic RAM.
Both are connected to the corresponding complementary bit lines of the memory arrays ARYL and ARYR via the corresponding shared MOSFET, respectively, and when the dynamic RAM is selected, one of them is selectively opened according to the internal address signal Xi. State.

A precharge MOSFET constituting a bit line precharge circuit of each unit circuit of the sense amplifier SA
When the dynamic RAM is set to the non-selection state, it receives the high level of the precharge control signal PC and is selectively and simultaneously turned on, and the non-inverting and inverting input / output nodes of the corresponding unit circuit, that is, the memory array The non-inverted and inverted signal lines of the complementary bit lines of ARYL and ARYR are precharged to the intermediate voltage HV between the internal voltage VDL and the ground potential VSS.

On the other hand, the unit amplifier circuit of each unit circuit of the sense amplifier SA includes sense amplifier drive signals PA1 and PA3.
Of the memory array ARYL or ARYR and the corresponding complementary bit from a predetermined number of memory cells coupled to the selected word line of the memory array ARYL or ARYR. The minute read signals output via the lines are amplified to form binary read signals in which the internal voltage VDL is at a high level and the ground potential VSS is at a low level.
The switch MOSFET of each unit circuit is connected to a bit line selection signal YS0 supplied from the Y address decoder YD.
YSn are selectively turned on in response to the high level of YSn, and selectively connected between the complementary input / output node of the corresponding unit amplifier circuit of the sense amplifier SA and the complementary common data line CD *.

In this embodiment, a dynamic RA
M employs a boost sensing method, and each unit circuit of the sense amplifier SA further includes a pair of boost capacitors provided between the non-inverted and inverted input / output nodes of each unit amplifier circuit and the boost control signal BST. Further, the dynamic RAM of this embodiment employs an overdrive sense system, and a common source line for supplying high-potential-side operation power to the unit amplifier circuit is initially provided with a non-inverting or inverting input / output node of each unit amplifier circuit. , The power supply voltage VCC higher than the internal voltage VDL is temporarily supplied. The specific configuration of the sense amplifier SA and the specific contents of the boost sense operation and the overdrive sense operation will be described later in detail.

The complementary common data lines CD * of the memory mats MAT0 to MAT7 are commonly connected to the output terminal of the corresponding write amplifier WA and the input terminal of the main amplifier MA, respectively. The input terminal of the write amplifier WA of each memory mat is coupled to the output terminal of the corresponding unit circuit of the data input buffer IB via the corresponding bit of the write data bus WDB0-WDB7, and the output terminal of the main amplifier MA of each memory mat. The terminal is connected to the read data bus RDB0.
RDB7 to the input terminal of the corresponding unit circuit of the data output buffer OB via the corresponding bit. An input terminal of each unit circuit of the data input buffer IB and an output terminal of each unit circuit of the data output buffer OB are commonly coupled to corresponding data input / output terminals D0 to D7, respectively. An internal control signal WP (not shown) is commonly supplied from a timing generation circuit TG to the write amplifiers WA of the memory mats MAT0 to MAT7, and an internal control signal OC is commonly supplied to each unit circuit of the data output buffer OB. .

Each unit circuit of the data input buffer IB includes:
When the dynamic RAM is set to the selected state in the write mode, 8-bit write data input through the data input / output terminals D0 to D7 is fetched and held, and the corresponding data is written via the write data buses WDB0 to WDB7. The signal is transmitted to the write amplifiers WA of the memory mats MAT0 to MAT7. At this time, the write amplifier WA of each memory mat is selectively activated in response to the high level of the internal control signal WP, and the write data buses WDB0 to WDB0 to WDB0 to WDB0 to
After the write data transmitted via DB7 is converted into a predetermined complementary write signal, the corresponding memory array ARYL is supplied from complementary common data line CD * via sense amplifier SA.
Alternatively, data is written into a selected one of ARYR, that is, a total of eight memory cells.

On the other hand, when the dynamic RAM is set to the read mode, the memory mats MAT0 to MAT7 supply complementary common data from a total of eight selected memory cells of the corresponding memory array ARYL or ARYR. The binary read signal output via the line CD * is further amplified and read data buses RDB0 to RDB0
The data is transmitted to the corresponding unit circuit of the data output buffer OB via the RDB 7. At this time, the data output buffer OB
Are selectively operated in response to the high level of the internal control signal OC, and the corresponding main amplifier MA
Read signals transmitted from the data input / output terminals D0 to D0
Output via D7.

The timing generation circuit TG generates various internal control signals and the like based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as a start control signal from an external access device. It is selectively formed and supplied to each part of the dynamic RAM.

Although not shown in FIG. 1, the dynamic RAM has predetermined internal voltages VPP and VDL and an intermediate voltage based on a power supply voltage VCC and a ground potential VSS supplied through predetermined external terminals. An internal voltage generation circuit for generating voltage HV is provided. Of these, the internal voltage VPP
Is mainly used as a selection level of a word line constituting the memory arrays ARYL and ARYR, and the internal voltage VDL
Are mainly used as an operating power supply for the memory arrays ARYL and ARYR and their direct peripheral circuits. Although not particularly limited, the power supply voltage VCC is set to a positive potential, for example, 2.5 V (volt). Also, the internal voltage VPP
Is set to, for example, 4.0 V, and the internal voltage VDL and the intermediate voltage HV are set to 1.5 V and 0.75 V, respectively.

FIG. 2 is a partial circuit diagram of one embodiment of the memory arrays ARYL and ARYR and the sense amplifier SA included in the memory mats MAT0 to MAT7 of the dynamic RAM of FIG. 1, and FIG. , A signal waveform diagram of the embodiment is shown. Based on these figures, memory mats MAT0-M
The specific configuration and operation of the memory arrays ARYL and ARYR and the sense amplifier SA that constitute the AT 7 and their characteristics will be described.

In the following description, a set of the memory arrays ARYL and ARYR and the sense amplifier SA will be taken as an example. However, the memory arrays ARYL and ARYR and the sense amplifier SA having the same configuration are connected to the memory mat MA.
Needless to say, they are included in each of T0 to MAT7 and operate similarly. In FIG. 3, a memory array ARYL provided on the left side of the sense amplifier SA is shown.
In which the word line WL0 is selected.
The description of the operation will proceed with a focus on the memory cell arranged at the intersection of the word line WL0 and the complementary bit line BL0 * and holding the data of logic "1". In the following circuit diagrams, MOSFETs with an arrow on their channel (back gate) portion are P-channel MOSFETs, which are distinguished from N-channel MOSFETs without an arrow.

In FIG. 2, the memory array ARYL is
M + 1 word lines WL0 to WLm arranged in parallel
And n + 1 sets of complementary bit lines BL0 * to BLn * arranged orthogonal to these word lines and parallel to each other. At the intersection of these word lines and complementary bit lines,
Information storage capacitor Cs and address selection MOSFET
(M + 1) × (n + 1) dynamic memory cells composed of Qa are arranged in a lattice. Memory array ARYL
Of the information storage capacitors Cs of the (m + 1) memory cells arranged in the same column are connected to complementary bit lines BL0 * to BL
The non-inverted or inverted signal lines of n * are alternately coupled with a predetermined regularity. Further, the address selection MO of n + 1 memory cells arranged on the same row of the memory array ARYL
The gate of the SFET Qa is connected to the corresponding word line WL0-W
Lm. Memory array ARYL
Storage capacitors C of all the memory cells constituting
The other electrode of s has a plate voltage of 0.75
V intermediate voltage HV is commonly supplied.

Similarly, the memory array ARYR includes (m + 1) word lines WR0 to WRm arranged in parallel and (n + 1) sets of complementary bit lines BR0 * arranged orthogonal to and parallel to each other. To BRn *.
At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) dynamic memory cells composed of an information storage capacitor Cs and an address selection MOSFET Qa are arranged in a lattice. One electrode of the information storage capacitor Cs of the (m + 1) memory cells arranged in the same column of the memory array ARYR has a corresponding address selection MOS.
Via the FET Qa, the complementary bit lines BR0 * to BRn * are alternately coupled to the non-inverted or inverted signal lines with a predetermined regularity. Further, the address selection MOSFE of n + 1 memory cells arranged in the same row of the memory array ARYR
The gates of TQa are commonly coupled to corresponding word lines WR0-WRm, respectively. The intermediate voltage HV is commonly supplied as a plate voltage to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array ARYR.

Next, the sense amplifiers SA are connected to the complementary bit lines BL0 * to BLn of the memory arrays ARYL and ARYR.
* And n provided corresponding to BR0 * to BRn *
+1 unit circuits, each of which comprises a P-channel MOSFET P2 and an N-channel M
OSFET N8 and P-channel MOSFET P3
And a pair of N-channel MOSFETs N9
A unit amplifier circuit in which OS inverters are cross-coupled is used as a basic component. Each unit circuit of the sense amplifier SA further includes three N-channel precharge MOs.
A bit line precharge circuit in which SFETs N5 to N7 are connected in series and parallel, and a pair of N-channel switches M
OSFETNA and NB, a pair of boost capacitors C1 and C2 each composed of a MOSFET capacitor, and corresponding complementary bit lines BL of the memory arrays ARYL and ARYR
0 * to BLn * and BR0 * to BRn *, each including two sets of first switches of N-channel type, that is, shared MOSFETs N3 and N4 and NC and ND, respectively.

A precharge MOSFET constituting a bit line precharge circuit of each unit circuit of the sense amplifier SA
The precharge control signal PC is commonly supplied from the timing generation circuit TG to the gates of N5 to N7, and the intermediate voltage HV is supplied to the commonly coupled sources of the precharge MOSFETs N6 and N7. The sources of the P-channel MOSFETs P2 and P3 constituting each unit amplifier circuit are commonly coupled to a common source line CSP (first common source line), and the sources of the N-channel MOSFETs N8 and N9 are connected to a common source line CSN (first common source line CSN). 2 common source lines). Common source line CSP
Is coupled to power supply voltage VCC via a P-channel type drive MOSFET P1 receiving a sense amplifier drive signal PA2B at its gate, and is an N-channel type drive MOSFET N receiving a sense amplifier drive signal PA3.
1 to internal voltage VDL. The common source line CSN has a sense amplifier drive signal PA1 at its gate.
, And is coupled to ground potential VSS via an N-channel type drive MOSFET N2.

On the other hand, the other one of the switch MOSFETs NA and NB of each unit circuit of the sense amplifier SA is commonly connected to a non-inverted or inverted signal line of the complementary common data line CD *, and the common-coupled gate has a Y gate. The corresponding bit line selection signals YS0 to YS from the address decoder YD
n are supplied respectively. The shared control signal SHL is commonly supplied from the timing generation circuit TG to the gates of the shared MOSFETs N3 and N4 of each unit circuit, and the gates of the shared MOSFETs NC and ND are
The shared control signal SHR is commonly supplied. further,
One of the boost capacitors C1 and C2 of each unit circuit, that is, an electrode on the gate side is coupled to the non-inverting input / output nodes S0T to SnT and the inverting input / output nodes S0B to SnB of the corresponding unit circuit, that is, the unit amplifier circuit, respectively. The other electrode, ie, the electrode on the drain / source side, is commonly coupled to the boost control signal BST.

Here, the precharge control signal PC is not particularly limited, but as shown in FIG. 3, is normally at a high level such as the power supply voltage VCC when the dynamic RAM is in the non-selection state. Dynamic type R
When AM is selected, it is set to a low level such as the ground potential VSS at a predetermined timing. In addition, shared control signals SHL and SHR are usually supplied with power supply voltage VCC.
When the dynamic RAM is set to the selected state, one of them, that is, for example, the shared control signal SHR is set to the low level such as the ground potential VSS according to the internal address signal Xi of the most significant bit. . Then, the remaining one, that is, the shared control signal SHL is set to a low level such as the ground potential VSS immediately before the boost sensing operation by the boost capacitors C1 and C2 is started, and then the boost sensing operation and the overdrive operation are completed. At the time, the potential is set to a high potential such as the internal voltage VPP, and when the dynamic RAM is set to the non-selected state, the potential is returned to the high level such as the power supply voltage VCC together with the shared control signal SHR.

On the other hand, word lines WL0 to WLm and W
Normally, R0 to WRm are all set to a non-selection level such as the ground potential VSS, and when the dynamic RAM is set to the selected state, it is selectively set to the selection level such as the internal voltage VPP according to the internal address signals X0 to Xi. You. The boost control signal BST is normally set to a low level such as the ground potential VSS. When the dynamic RAM is set to the selected state, the word line selecting operation is completed and the shared control signal SST is set.
Immediately after both HL and SHR are set to the low level, they are set to the high level such as the power supply voltage VCC.

The sense amplifier drive signal PA1 is normally set to a low level such as the ground potential VSS, and when the dynamic RAM is selected, the boost capacitors C1 and C2 are set.
At the end of the boost operation by the power supply voltage VCC. The sense amplifier drive signal PA2B is set to a high level such as the normal power supply voltage VCC, and when the dynamic RAM is selected, the sense amplifier drive signal PA2B is temporarily synchronized with the rise of the sense amplifier drive signal PA1 for a predetermined period. It is set to a low level such as the ground potential VSS. Further, the sense amplifier drive signal PA3
Is normally at a low level such as the ground potential VSS, and when the dynamic RAM is selected, the high potential of the high potential such as the internal voltage VPP is synchronized with the return of the sense amplifier drive signal PA2B to the high level. Level.

When the dynamic RAM is set to the non-selection state and the shared control signals SHL and SHR are set to the high level such as the power supply voltage VCC, in the sense amplifier SA, the shared MOSFETs N3 and N4 and NC and ND of all the unit circuits are changed. They are simultaneously turned on. At this time, the precharge control signal PC is set to a high level such as the power supply voltage VCC, and in response to this, the precharge MOSFE configuring the bit line precharge circuit of each unit circuit.
TN5 to N7 are simultaneously turned on.

Thus, the non-inverting and inverting input / output nodes of the complementary input / output nodes S0 * to Sn * of each unit circuit of the sense amplifier SA, the complementary bit lines BL0 * to BLn * and BR0 * to the memory arrays ARYL and ARYR. BR
All the n * non-inverted and inverted signal lines are precharged to the intermediate voltage HV. Also, the sense amplifier drive signal PA
1 and PA3 and the high level of the sense amplifier drive signal PA2B, the drive MOSFET N
1 and N2 and P1 are all turned off, and the common source lines CSP and CSN are precharged to an intermediate voltage HV via a common source line precharge circuit (not shown). The drain-source electrodes of the boost capacitors C1 and C2 of each unit circuit of the sense amplifier SA receive the low level of the boost control signal BST and receive the ground potential VS.
S is charged.

When the dynamic RAM is set to the selected state, the precharge control signal PC is first set to a low level such as the ground potential VSS at a predetermined timing, and the precharge control signal PC is precharged by the bit line precharge circuit of each unit circuit of the sense amplifier SA. The charging operation is stopped. Subsequently, for example, the unselected memory array AR not including the designated word line WL0
Shared control signal SHR corresponding to YR is at ground potential VS
S, the shared MOSFETs NC and ND of each unit circuit of the sense amplifier SA are simultaneously turned off, and the complementary input / output nodes S0 * to Sn * and the complementary bit lines BR0 * to BRn of the memory array ARYR are turned off. *
The connection to is broken.

In the memory array ARYL, when the decoding operation of the X address decoder XDL is completed, the word line WL0 designated by the internal address signals X0 to Xi
Are alternatively set to a high potential selection level such as the internal voltage VPP, and the other word lines WL1 to WLm are all kept at a non-selection level such as the ground potential VSS. Thereby, the complementary bit lines BL0 * of the memory array ARYL
To BLn *, that is, the complementary input / output nodes S0 * to Sn * of the sense amplifier SA, output the minute read signals corresponding to the data held in the (n + 1) memory cells coupled to the selected word line WL0. As a result, for example, the potential of the non-inverting signal line BL0T of the complementary bit line BL0 * to which the memory cell holding the data of logic "1" is coupled, that is, the potential of the non-inverting input / output node S0T of the complementary input / output node S0 * slightly increases. However, the potential is slightly higher than the potential of the inverted signal line BL0B, that is, the inverted input / output node S0B.

When the word line selecting operation is completed, for example, complementary bit lines BL0 * to BLn * of memory array ARYL, that is, complementary input / output nodes S0 * to Sn * of sense amplifier SA.
When the small read signal of the (n + 1) memory cells coupled to the selected word line WL0 is completely output, first, the shared control signal SHL corresponding to the designated memory array ARYL
Is set to a low level such as the ground potential VSS, and then the boost control signal BST is set to a high level such as the power supply voltage VCC. Also, with a slight delay, the sense amplifier drive signal P
A1 is set to a high level like the power supply voltage VCC, and at the same time, the sense amplifier drive signal PA2B is temporarily set to a low level like the ground potential VSS. Then, when a predetermined time has elapsed, the sense amplifier drive signal PA2B
Is returned to the high level like the power supply voltage VCC, and at the same time, the sense amplifier drive signal PA3 is set to the high level like the internal voltage VPP.

The sense amplifier SA receives the low level of the shared control signal SHL and receives the shared M of each unit circuit.
The OSFETs N3 and N4 are turned off, and the connection between the complementary input / output nodes S0 * to Sn * and the complementary bit lines BL0 * to BLn * of the memory array ARYL is disconnected. Also, in response to the high level of the boost control signal BST, the drain / source electrodes of the boost capacitors C1 and C2 of each unit circuit are boosted to the power supply voltage VCC, and in response to this, the complementary input / output nodes S0 * to Sn * The potential of the non-inverting and inverting input / output nodes is boosted by an amount corresponding to the charge share between the capacitances of the boost capacitors C1 and C2 and the parasitic capacitance of each input / output node. At this time, the boost capacity C1
And the capacitance value of C2 becomes smaller because the drain / source side potential is in a reverse bias state higher than the gate potential,
Correspondingly, the voltage between both electrodes increases, the potential difference between the non-inverting and inverting input / output nodes of the corresponding complementary input / output nodes S0 * to Sn * slightly increases, and the signal amount increases.

Next, the sense amplifier SA receives the high level of the sense amplifier drive signal PA1 and drives the drive MOSFET FE.
TN2 is turned on, the low-potential-side operation power supply, that is, the ground potential VSS, is supplied to the common source line CSN, and the drive MOSFET P1 is turned on in response to the low level of the sense amplifier drive signal PA2B, and the common source line CSP includes: A power supply voltage VCC having an absolute value larger than that of a normal high-potential-side operation power supply is supplied. As a result, each unit amplifier circuit of the sense amplifier SA enters a so-called overdrive state, and starts an amplification operation in order to rapidly increase the potential difference between the non-inverting and inverting input / output nodes of the complementary input / output nodes S0 * to Sn *. Therefore, for example, the potential of the non-inverting input / output node S0T rapidly rises toward the power supply voltage VCC, and the potential of the inverting input / output node S0B changes to the ground potential VS.
It decreases toward S. However, since the sense amplifier drive signal PA2B returns to the high level after a predetermined period as described above, the potential rise of the non-inverting input / output node S0T is stopped halfway, and the sense amplifier drive signal PA3 receives the high level of the sense amplifier drive signal PA3. After the drive MOSFET N1 is turned on, the internal voltage VDL slightly decreases with the target potential.

As described above, complementary input / output node S0 *
The potential of the non-inverting and inverting input / output nodes of Sn * is boosted by a predetermined level by the boost capacitors C1 and C2, and the potential difference is slightly enlarged. Also,
When the common source line CSP is overdriven, for example, the high level of the non-inverting input / output node S0T corresponding to the memory cell holding the data of logic “1” is temporarily increased to exceed the internal voltage VDL. From these facts, the so-called pull-down N-channel MO
The drain-source voltages of the SFETs N8 and N9 increase, and the speed of the amplification operation is increased. The drain-source voltages of the pull-up P-channel MOSFETs P2 and P3 also increase, and the amplification operation is accelerated. You. As a result, the potential difference between the non-inverting and inverting input / output nodes, that is, the signal amount is increased, and the amplification operation of each unit amplifier circuit of the sense amplifier SA is accelerated, whereby the read operation of the dynamic RAM is accelerated. You.

When the amplification operation of each unit amplifier circuit of the sense amplifier SA is completed to some extent and the shared control signal SHL is returned to a high potential such as the internal voltage VPP, the complementary input / output node S0 of each unit circuit of the sense amplifier SA is returned. * ~ Sn
* And complementary bit lines BL0 * to B of memory array ARYL
Ln * is again connected, and the sense amplifier SA
Of the memory array ARYL, for example, the word line WL0 of the memory array ARYL.
Are rewritten to the (n + 1) memory cells coupled to. Also, bit line selection signals YS0 to YS (not shown)
n, the binary read signal of one designated memory cell is supplied to the complementary common data line CD *.
Is transmitted to the main amplifier MA through the data output buffer OB through the data input / output terminals D0 to D7, and when the dynamic RAM is selected in the write mode, the write amplifier The WA is brought into an operating state, and a write operation of new storage data supplied from the data input / output terminals D0 to D7 via the data input buffer IB is started.

As described above, in the sense amplifier SA of this embodiment, overdrive sensing is performed. For example, the potential of the non-inverting input / output node S0T is in an excessive overdrive state and its final high level, that is, the internal voltage It may be higher than VDL. However, in the dynamic RAM of this embodiment, the overdrive sense of the sense amplifier SA is caused by the shared MOSFET N on both sides.
3 and N4 and NC and ND are all turned off, so that the potential of the non-inverting input / output node SOT in the excessive overdrive state becomes the shared MOSF again.
When ETN3 and N4 are turned on, charge sharing is performed between the complementary bit lines BL0 * to BLn * of the memory array ARYL to approach the internal voltage VDL. As a result, the power consumption required for the overdrive sense of the sense amplifier SA can be reduced, the power consumption of the dynamic RAM can be reduced, and the inversion write operation by the write amplifier WA can be realized reliably and at high speed. Becomes

The functions and effects obtained from the above embodiments are as follows. (1) In a dynamic RAM or the like that uses a boost sense method and a shared sense method, all the shared MOSFETs are kept off after the non-inverting of the unit amplifier circuit and the inverting input / output nodes have been boosted by the boost capacitance. Overdrive operation of the unit amplifier circuit increases the drain-source voltage of the N-channel MOSFET constituting each unit amplifier circuit of the sense amplifier by the boost sense operation, and increases the drain-source voltage of the P-channel MOSFET by the overdrive operation. The effect of increasing the voltage and accelerating the amplification operation of the unit amplifier circuit can be obtained. (2) According to the above item (1), an effect is obtained that the reading operation of a dynamic RAM or the like can be speeded up.

(3) In the above items (1) and (2), during overdrive operation, the corresponding complementary bit line of the memory array is disconnected from the complementary input / output node of each unit amplifier circuit to reduce the load. Is obtained. (4) According to the above item (3), the effect that the power consumption of the dynamic RAM can be reduced can be obtained. (5) According to the above (3) and (4), the shared MO
When the SFET is turned off, the potential of the non-inverted or inverted input / output node of the overdriven unit amplifier circuit can be reduced by charge sharing with the parasitic capacitance of the corresponding complementary bit line of the memory array. Is obtained. (6) According to the above item (5), an effect is obtained that the inversion and rewriting operation of stored data can be performed reliably and at high speed while further reducing the power consumption of a dynamic RAM or the like. (7) According to the above items (1) to (6), the dynamic R
It is possible to obtain an effect that the operating power supply such as the AM is sufficiently lowered in voltage, the rise in the chip temperature is suppressed, and the refresh characteristics of the dynamic RAM or the like can be greatly improved.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can have an arbitrary number of memory mats, and the memory arrays ARYL and ARYR constituting each memory mat are divided into a plurality of sub-arrays including their immediate peripheral portions. Can be. A dynamic RAM is a × 1 bit or × 1 bit.
An arbitrary bit line configuration such as 6 bits can be adopted, and adopting a shared sense system is not an essential condition. In this case, a switch equivalent to a shared MOSFET is required between the sense amplifier and the memory array. Y
The address decoder YD may be provided commonly to all or a predetermined number of memory mats. Dynamic RAM is
Any block configuration can be adopted. The names and combinations of the start control signals, the names and effective levels of each control signal, and the polarities and absolute values of the power supply voltage and each internal voltage are
Various embodiments can be adopted.

In FIG. 2, the memory arrays ARYL and ARYR and the sense amplifier SA can include a predetermined number of redundant elements. Further, the memory arrays ARYL and ARYR can adopt a so-called word line division system in which main word lines and sub word lines are hierarchically used. The drive MOSFETs P1 and N1 and N2 of the sense amplifier SA may be composed of a plurality of drive MOSFETs each in a parallel form, or may be an ON state while shifting the plurality of drive MOSFETs in time series. There may be. Boost capacity C1 and C2
Can be replaced with a plurality of MOSFET capacitors each in a parallel configuration. Specific Configuration of Memory Arrays ARYL and ARYR and Sense Amplifier SA and M
Various embodiments can be adopted for the conductivity type and the like of the OSFET. In FIG. 3, the absolute potential and time relationship of each signal does not affect the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device employing a boost sense method and a device or system including the same.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that employs a boost sense system and a shared sense system, after the non-inverting of the unit amplifier circuit and the inverting input / output node have been boosted by the boost capacitance, the shared MOS
Overdrive operation of the unit amplifier circuit with all FETs in the off state increases the drain-source voltage of the N-channel MOSFETs that make up each unit amplifier circuit of the sense amplifier by boost sense operation. P channel MOS
By increasing the drain-source voltage of the FET to speed up the amplification operation of each unit amplifier circuit, a dynamic RAM
Etc. can be speeded up. Further, at the time of the overdrive operation, the corresponding complementary bit line of the memory array is disconnected from the complementary input / output node of each unit amplifier circuit, the load can be reduced, and the dynamic RAM and the like can be reduced in power consumption. Shared M
When the OSFET is returned to the ON state, the potential of the non-inverted or inverted input / output node of the overdriven unit amplifier circuit is reduced by charge sharing with the parasitic capacitance of the corresponding complementary bit line of the memory array, and the storage data Inversion rewriting can be performed reliably and at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 3 is a signal waveform diagram showing one embodiment of a memory array and a sense amplifier of FIG. 2;

FIG. 4 is a partial circuit diagram showing an example of a memory array and a sense amplifier included in a dynamic RAM studied by the present inventors prior to the present invention.

FIG. 5 is a signal waveform diagram illustrating an example of a memory array and a sense amplifier in FIG. 4;

[Explanation of symbols]

MAT0 to MAT7: Memory mat, ARYL, AR
YR memory array, XDL, XDR X address decoder, XB X address buffer, SA sense amplifier, YD Y address decoder, YB Y
Address buffer, WA: Write amplifier, MA: Main amplifier, IB: Data input buffer, OB: Data output buffer, TG: Timing generation circuit. D0
~ D7 ... I / O data or its I / O terminal, RASB
... Row address strobe signal or its input terminal, C
ASB: a column address strobe signal or its input terminal; WEB: a write enable signal or its input terminal; A0 to Ai: an address signal or its input terminal. W
L0 to WLm, WR0 to WRm ... word line, BL0 *
To BLn *, BR0 * to BRn *... Complementary bit line, Q
a: Address selection MOSFET, Cs: Information storage capacitor, S0 * to Sn *: Sense amplifier complementary input / output node, CSP, CSN: Common source line, CD *
... Complementary common data line, HV ... Intermediate voltage, SHL, SH
R: Shared control signal, PC: Precharge control signal, PA, PA1B, PA2B, PAB: Sense amplifier drive signal, BST: Boost control signal, YS0 to Y
Sn: a bit line selection signal. P1 to P4: P-channel MOSFET, N1 to ND: N-channel MOSF
ET, C1 to C2 ... Boost capacity. VCC: power supply voltage, VSS: ground potential, VPP, VDL: internal voltage.

Claims (3)

[Claims] A memory array including a word line and a complementary bit line; a unit amplifier circuit provided corresponding to the complementary bit line; and a complementary bit line corresponding to a complementary input / output node of the unit amplifier circuit. And a small read signal of a memory cell provided between a complementary input / output node of the unit amplifier circuit and a boost control signal line and coupled to a selected word line. A boost capacitor that boosts the potential of the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit at the time of being output to the corresponding complementary bit line, and selectively supplying a high-potential side and a low-potential-side operating power supply to the unit amplifier circuit And a sense amplifier including first and second common source lines to be supplied, and a high-potential side supplied through the first common source line. Potential of work power in the initial predetermined period of time of driving,
A semiconductor memory device which is temporarily overdriven to have a potential higher than a final high level at a non-inverted or inverted input / output node of the unit amplifier circuit. 2. The memory array according to claim 1, wherein the memory array is provided on both sides of the sense amplifier, and wherein the first switch means comprises a complementary input / output node of each unit amplifier circuit of the sense amplifier and the memory array. A booster circuit for boosting the potential of the boost capacitor and the first memory cell, the memory cell array being provided between corresponding complementary bit lines of the memory array provided on both sides;
The overdrive operation of the common source line
The semiconductor memory device is performed while all of the switch means are turned off. 3. The first switch according to claim 1, wherein a potential at a non-inverting or inverting input / output node of the unit amplifier circuit, which is higher than a final high level by the overdrive operation, is equal to the first switch. A semiconductor memory device characterized in that when the means is returned to the ON state, the charge is shared between the corresponding complementary bit line and the final high level.