JPH1013012A - Semiconductor package and semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor package and a semiconductor device capable of securing the height of a solder bump when an IC chip is mounted. SOLUTION: Since a resin spacer 50 is arranged in a solder bump region, a solder bump 49 is not crushed when solder 48, 62 is heated and melted. Since the height of the solder bump 49 can be secured by the resin spacer 50, the solder 48,
With 62, the difference in the coefficient of thermal expansion between the IC chip 60 made of silicon and the semiconductor package 10 made of resin can be absorbed, and the occurrence of cracks on the semiconductor package 10 can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a semiconductor device, and more particularly to a semiconductor package and a semiconductor device capable of preventing a crack from occurring in a portion where an IC chip is mounted.

[0002]

2. Description of the Related Art In recent years, in order to increase the number of connection terminals per area, a mounting method called flip-chip mounting, in which an IC chip is directly mounted on a semiconductor package via solder bumps and sealed with resin, has been adopted. I have. However, in such a mounting method, the thermal expansion coefficient of the IC chip made of silicon is different from the thermal expansion coefficient of the resin substrate side.
There has been a problem that cracks occur on the substrate side due to the heat cycle. For this reason, attempts have been made to increase the height of the solder bumps connecting the IC chip and the semiconductor package so that the solder functions as a buffer material to absorb the difference in the coefficient of thermal expansion.

[0003] This method will be described with reference to FIG. IC
Solder bumps 164 made of high melting point solder 162 are formed on the electrodes 166 on the chip 60 side, and solder bumps 149 made of low melting point solder 148 are formed on the semiconductor package 210 side. When heated at a low temperature, only the low melting point solder 148 is melted and crushed, and the high melting point solder 162 is not melted and the bump shape remains.
2, the height of the solder bump is secured. The difference between the coefficients of thermal expansion is absorbed by increasing the distance between the IC chip 60 and the semiconductor package 210 by the height of the solder bumps 164 formed of the remaining high melting point solder 162.

[0004]

However, there is a limit to increasing the height of the solder bump made of the high melting point solder on the IC chip side. This is because the solder bumps are usually spherical, and if the height is increased, the diameter of the sphere is increased, so that the adjacent solder bumps inevitably come into contact. Also, when the diameter of the solder bump is increased, the number of terminals that can be connected per area decreases, and it becomes impossible to achieve a fine pitch. For this reason, the interval between the solder bumps is the limit of the height.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor package and a semiconductor package which can secure the height of a solder bump when an IC chip is mounted. It is to provide a semiconductor device.

[0006]

In order to achieve the above object, a first aspect of the present invention is a semiconductor package in which a solder bump group for mounting a semiconductor component is formed on a wiring board. A technical feature is that a solder body is provided and formed on a connection pad made of a metal conductor, and a resin spacer for securing a space between the semiconductor component and the connection pad is provided in a region of the solder bump group.

In the present invention, the conventional idea that the height is secured by the solder bump itself is abandoned, and it is intended to realize it by the resin spacer. In the present invention, since the resin spacer is arranged in the solder bump area, the solder bump is not crushed even when the solder is heated and melted, and the solder bump on the semiconductor package side and the IC chip can be formed without increasing the solder bump diameter. If the solder bumps are large enough to make contact with the solder bumps on the side, the connection can be made while ensuring a sufficient height of the solder. Since the height of the solder bump can be ensured by the resin spacer, the difference in the coefficient of thermal expansion between the IC chip side and the semiconductor package side can be absorbed by this solder, and the occurrence of cracks on the semiconductor package side can be suppressed.

In the present invention, it is desirable that at least a part of the connection pad is formed as a via hole, and a resin spacer is formed by filling a concave portion of the via hole with a resin. The via hole is formed by providing a plating film for connecting the inner layer conductor circuit and the surface layer conductor circuit to an opening provided in an interlayer insulating material layer for insulating the surface layer conductor circuit and the inner layer conductor circuit.

For this reason, by filling the concave portion of the via hole with the resin, the resin does not flow in the horizontal direction and becomes spherical due to surface tension, so that a high resin spacer can be formed with a small amount of resin. Further, since the via hole is made of metal, it can be easily recognized optically even when it is automatically injected with a dispenser or the like, and serves as a target mark.
It is desirable that the resin is filled at four corners of the solder bump group that are diagonal to each other (see FIG. 5B). This is because this location can most stably support the IC chip.

According to the present invention, a resin spacer can be formed between the solder bumps constituting the solder bump group. For example, it is possible to provide a resin spacer between the solder bumps, or to replace a specific row of solder bumps with the resin spacer. Such a resin spacer can be manufactured by printing an uncured resin by a method such as screen printing and heating and curing the resin. Alternatively, a photosensitive resin may be applied, only the area where the resin spacer is to be formed is exposed, and the exposed area may be subjected to a developing process.

In the present invention, the resin spacer is desirably a semi-cured resin. The reason is that when mounting a semiconductor component such as an IC chip, it can be adjusted to an appropriate height by applying heat and pressure. Further, before mounting the semiconductor component, flattening (fluttering) can be performed by applying heat and pressure using a flat plate in advance.

The resin spacer is made of epoxy resin, polyimide resin, epoxy-PES (polyethersulfone) composite resin, epoxy acrylate resin, epoxy-
Epoxy acrylate resin. Desirably, it is at least one selected from silicone resins and thermoplastic resins such as PES and PS (polysulfone). Especially,
Epoxy-epoxy acrylate resins are preferred. The reason for this is that the shape of the spherical resin spacer can be easily maintained by light curing, and since it is in a semi-cured state, fluttering is possible and height control can be performed with high precision.

In the present invention, it is desirable that a semiconductor component is electrically connected to the semiconductor package via solder bumps, and that a distance between the semiconductor package surface and the semiconductor component is adjusted to 50 to 100 μm by a resin spacer. . If the interval is less than 50 μm, the height of the solder is too small and there is no crack preventing effect. On the other hand, if the interval exceeds 100 μm, the fixing strength of the solder decreases, and the IC chip is easily detached. After the IC chip is mounted, the resin is suctioned by capillary action to seal the solder connection portion with the resin.

[0014]

Next, a method for manufacturing a semiconductor package according to a first embodiment will be specifically described with reference to the drawings. The manufacturing method is not limited to this. The semiconductor package includes the following steps 1) to 6). 1) A step of obtaining a substrate on which a conductor circuit is formed. 2) forming an interlayer insulating layer; 3) forming a hole for a via hole in the interlayer insulating material layer; 4) A step of forming a conductor pattern, a solder bump pad, and a via hole on the surface of the interlayer insulating layer. 5) A step of forming a solder body in a solder bump pad and a via hole to form a solder bump. 6) A step of forming a resin spacer such as a part of a via hole or between solder bumps.

FIGS. 1 to 4 show a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention. First,
In step 1), a core base material or a build-up multilayer substrate manufactured by etching a copper-clad laminate is obtained.

In this case, as shown in FIG.
a copper-clad laminate 20a formed by laminating a 18 μm copper foil 22 on both sides of a substrate 20 made of glass epoxy or BT (bismaleimide triazine) of 20 mm;
By etching the copper foil 22 in a pattern according to a conventional method, inner layer copper patterns 24a are formed on both surfaces of the substrate 20, as shown in FIG. Further, as shown in FIG. 1C, a through hole 27 for a through hole is formed, and a copper plating 25 is applied to form a through hole 28.

On the other hand, a bisphenol F epoxy monomer (manufactured by Yuka Shell Epoxy: molecular weight 310: trade name E-
100 parts by weight of 807), an imidazole curing agent (made by Shikoku Kasei Co., trade name: 2E4MZ-CN) 6 parts by weight, further, to this mixture, the average diameter 1.6μm of SiO ₂ spherical particles
(Here, the maximum grain is 15 μm or less of the thickness of the inner layer copper pattern 24a described later), and 170 parts by weight are mixed.
Knead with this roll, viscosity at 23 ± 1 ° C 55 ± 10
Prepare resin for flattening Pa · s. This resin is solvent-free. If a resin containing a solvent is used, if an interlayer agent is applied and heated and dried, the solvent will evaporate from the resin layer for flattening, and peeling will occur between the resin layer for flattening and the interlayer material. Because you do.

Here, as shown in FIG. 1D, the above resin is applied to the substrate 20 by a roll coater to fill the through holes 28 between the conductor circuits (inner layer copper patterns 24a). Then, it is cured by heating at 150 ° C. for 30 minutes. After this heat treatment, the above-mentioned filling resin 26
By heating at 50 ° C. for 3 hours, the film is almost completely crosslinked and has a high hardness. However, as described later, the polishing is performed by curing only in a range where belt sander polishing or buffing is possible. Make the work easy. By this step, the filling resin 26 is filled between the inner layer copper patterns 24a.

Subsequently, one side of the substrate 20 is polished with a belt sander using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). At this time, polishing is performed so that the filling resin 26 does not remain on the inner layer copper pattern 24a and the land 28a of the through hole 28. Thereafter, buffing is performed to remove the scratches caused by the belt sander. Then, the other surface is similarly polished to form a flat substrate 20 on both surfaces as shown in FIG. Thereafter, the filling resin 26 is completely cross-linked by heating at 150 ° C. for 3 hours. Here, the inner layer copper pattern 24 using a belt sander is used.
Polishing was performed so that the flattening resin did not remain on the surface of the land 28a of the hole a or the through hole. The remaining resin can be completely removed by buffing. Further, the flattening resin may be completely removed only by buffing.

The flattening resin containing the SiO ₂ spherical particles according to the above-described composition has a small curing shrinkage.
The substrate 20 does not warp. Further, since the coefficient of linear thermal expansion is reduced, the resistance to heat cycles is excellent.

As described above, in the first embodiment, if necessary, between the conductor patterns on the surface of the core substrate, through holes,
At least one location selected from via holes is filled with a resin filler. Conductor pattern (inner layer copper pattern) 24a
Has irregularities. For this reason, resin filler 2 for flattening
After uniformly coating 6 on the substrate, it is cured and the surface of the substrate is polished and smoothed. In order to form an interlayer insulating layer on the smoothed surface of the substrate 20 as described later,
The thickness of the interlayer insulating agent layer can be made uniform. That is,
As described below, the interlayer insulating agent disposed at a uniform thickness is exposed and developed to form via holes, so that any via holes can be exposed under the same exposure conditions, and the via holes can be unopened or shaped. No defect is generated.

In step 2), an interlayer insulating layer is formed.
Here, the interlayer insulating agent is composed of two layers, the lower layer is a heat-resistant resin layer hardly soluble in an acid or an oxidizing agent, and the upper layer is
An adhesive layer for electroless plating in which resin particles soluble in an acid or an oxidizing agent are dispersed in a heat-resistant resin matrix hardly soluble in an acid or an oxidizing agent is desirable.

First, a hardly heat-resistant resin matrix in which soluble resin particles are dispersed is produced. Cresol novolak type epoxy resin dissolved in DMDG (dimethyl glycol dimethyl ether) (manufactured by Nippon Kayaku: molecular weight 2)
70), 25 parts by weight of a 25% acrylated product of (500), 30 parts by weight of polyether sulfone (PES), 4 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals), and a caprolactone-modified Tris (acrochemical) as a photosensitive monomer. Xylethyl) isocyanurate (Toa Gosei:
10 parts by weight of Aronix M325), 5 parts by weight of benzophenone as a photoinitiator (manufactured by Kanto Kagaku), 0.5 parts by weight of Michler's ketone as a photosensitizer (manufactured by Kanto Kagaku), and an epoxy resin to this mixture After mixing 35 parts by weight of particles having an average particle diameter of 5.5 μm and 5 parts by weight of particles having an average particle diameter of 0.5 μm, mixing was further performed while adding NMP, and the viscosity was adjusted to 2000 cps with a homodisper stirrer. To obtain a photosensitive adhesive (interlayer resin insulating material).

The substrate 20 that has been subjected to the polishing step described above with reference to FIG.
Is acid degreased and soft-etched, treated with a catalyst solution composed of palladium chloride and an organic acid, a Pd catalyst is applied, activated, plated in an electroless plating bath,
Copper conductor (copper pattern) 24a and via hole pad 2
A 2.5 μm-thick uneven layer (roughened surface) of a Ni—P—Cu alloy is formed on the surface of 8a (not shown). Then, the substrate 20 is washed with water, and the substrate 20 is immersed in an electroless tin plating bath made of a tin borofluoride-thiourea solution at 50 ° C. for 1 hour.
A tin-substituted plating layer having a thickness of 0.3 μm is formed on the roughened surface of the i-Cu-P alloy (not shown).

Further, a photosensitive adhesive is applied to both sides of the substrate 20 using a roll coater, and the photosensitive adhesive is applied in a horizontal state.
After leaving for 30 minutes, drying is performed at 60 ° C. for 30 minutes to form an adhesive layer 32 having a thickness of 60 μm as shown in FIG. In addition to the configuration in which the photosensitive adhesive layer is formed directly on the filling resin 26, there is also a form in which an insulating material layer is formed and the photosensitive adhesive layer is formed thereon.

As the insulating material, 25% by weight of cresol novolak epoxy resin (70% by weight of Nippon Kayaku), 25% by weight of polyether sulfone (Mitsui Toatsu), 4% by weight of benzophenone, 0.4% by weight of Michler's ketone % And an imidazole-based curing agent, the mixture is adjusted to a viscosity of 30 Pa · s with a homodisper stirrer while adding N-methylpyrrolidone (NMP), and further kneaded with three rolls.

This is applied and dried, and then the above-mentioned photosensitive adhesive (a hardly soluble heat-resistant resin matrix in which soluble resin particles are dispersed) is applied to form an insulating material as shown in FIG. Two layers, a layer 34 and an adhesive layer 32, are formed.

In step 3), a hole for a via hole is formed. First, in order to form a via hole in the substrate 20 on which the adhesive layer 32 and the insulating material layer 34 are formed, 100 μm
A photomask film on which a black circle of φ is printed is brought into close contact with the photomask film, and exposed at 500 mj / cm ² using an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Further, the substrate 20 is subjected to 3000
exposed with mj / cm ^2, 1 hour at 100 ° C, then 150
By heat treatment at 5 ° C. for 5 hours, a 50 μm-thick resin interlayer insulating layer having openings (openings for forming via holes) 36 having excellent dimensional accuracy corresponding to a photomask film as shown in FIG. 35 (here,
The adhesive layer 32 and the insulating material layer 34 are collectively referred to as a resin interlayer insulating layer 35). A tin plating layer (not shown) is partially exposed in the opening 36 serving as a via hole. The opening 36 can be formed by laser in addition to the above-described exposure and development processing.

In step 4), a conductor pattern, pads for solder bumps, and via holes are formed. First, the substrate 20 in which the openings 36 are formed is immersed in chromic acid for 1 minute to dissolve the epoxy resin particles in the resin interlayer insulating layer 35, and
As shown in (I), the surface of the resin interlayer insulating layer 35 is roughened, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. By applying a palladium catalyst (manufactured by Atotech) to the substrate 20 that has been subjected to the surface roughening treatment, a catalyst nucleus is attached to the resin interlayer insulating layer 35 and the via hole opening 36.

In the interlayer insulating layer 35 of the present embodiment, the surface is roughened by dissolving and removing the resin particles with an acid or an oxidizing agent.
The adhesiveness with the conductor formed on the roughened surface is improved. For this reason, the upper layer (insulating material layer) 34 is formed by dispersing resin particles to be dissolved and removed in the adhesive layer for electroless plating, and the lower layer (adhesive layer) 32 is formed of a resin which is hardly dissolved in an acid or an oxidizing agent.
This prevents the upper layer 34 from dissolving too much and reaching the conductor in the lower layer 32. Since the resin 26 is filled between the conductor patterns 24a so that the surface thereof is flush with the surface of the conductor, the thickness of the interlayer insulating agent 35 can be made uniform. That is, since the via holes 44 described later are formed in the interlayer agent 35 provided with a uniform thickness, no defective via holes are generated.

On the other hand, a liquid resist is manufactured. Here, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., trade name: EOCN-103S) dissolved in DMDG was used to sensitize 25% of the epoxy groups of an acrylated oligomer (molecular weight 4000), PES (molecular weight 1700)
0), imidazole curing agent (Shikoku Chemicals: 2PM)
HZ-PW), an acrylic isocyanate that is a photosensitive monomer (manufactured by Toagosei Co., Ltd .: trade name ARONIX M21)
5), benzophenone as photoinitiator (Kanto Chemical), Michler's ketone as photosensitizer (Kanto Chemical)
Is mixed with NMP using the following composition, adjusted to a viscosity of 3000 cps with a homodisper stirrer, and then kneaded with three rolls. Resin composition; photosensitive epoxy / PES / M215 / BP
/MK/imidazole=70/30/10/5/0.5
/ 5

The liquid resist is applied using a roll coater to both surfaces of the substrate 20 which has been subjected to the above-described treatment for providing catalyst nuclei with reference to FIG. 2 (I), and dried at 60 ° C. for 30 minutes. A resist layer having a thickness of 30 μm is formed. Then
A mask film on which a conductor circuit pattern of L / S (ratio between line and space) = 50/50 is adhered,
Exposure at 1000 mj / cm ² with ultra high pressure mercury lamp, DMTG
To form a plating resist on which the conductor circuit pattern has been removed on the substrate 20, and further exposed to 6000 mj / cm ² using an ultra-high pressure mercury lamp.
A heat treatment is performed at 0 ° C. for 1 hour and then at 150 ° C. for 3 hours to form a permanent resist 38 on the interlayer insulating layer as shown in FIG.

The substrate 2 on which the permanent resist 38 is formed
0, a plating pretreatment (specifically, a sulfuric acid treatment or the like and activation of the catalyst nucleus) is performed in advance, and thereafter, the electroless copper plating bath is used for electroless plating to form a film having a thickness of 15 mm on the resist non-formed portion.
By depositing an electroless copper plating 40 of about μm and forming an outer layer copper pattern 42 and a via hole 44,
As shown in FIG. 2K, a conductor layer is formed by an additive method.

The conductor layer formed by the additive method is polished on one side with a belt sander using # 600 belt abrasive paper. At this time, polishing is performed until the surface layer of the permanent resist 38 and the uppermost surface of the copper in the via hole 44 are aligned. After that, buffing is performed to remove the scratches caused by the belt sander (only buffing may be performed). Then, the other surface is similarly polished to form a flat printed circuit board on both surfaces.

By repeating the above-described steps, a further conductive layer is formed by the additive method. By building up the wiring layers in this manner, a six-layered multilayer printed wiring board (FIG. 3L) is formed. In addition, on the upper surface in the figure of this multilayer printed wiring board,
Solder bump connection pads formed of via holes 44 for mounting an IC chip are formed as described later.

The substrate 20 is coated with a solder resist 46, exposed and developed, and an opening 46a larger than the pad diameter is formed on the IC chip mounting side (upper surface in the figure), and the pad diameter is formed on the connection side with the mother board. Smaller openings 46b are provided (FIG. 3M). In addition, via hole 4
4 is plated with nickel and gold in this order (not shown).

In step 5), a solder body is formed in a solder bump pad and a via hole to form a solder bump. Specifically, a solder transfer method (a resin film on which a solder pattern is formed is placed so that the solder pattern is in contact with a solder bump pad (via hole), and then heated and melted to form a solder ball and transfer. Method) or screen printing of a solder paste and heating to form solder bumps as solder balls (solder bodies).

In this embodiment, a solder transfer method is used. That is, a film having a solder pattern obtained by etching a solder foil on the surface of a polyethylene terephthalate film is placed so as to be in contact with the pads (via holes) 44, and the pads 44z for solder bumps at the four corners are left. This is heated and melted to transfer the solder 48 to the solder bump group 4.
9G is formed (FIG. 3 (N)). FIG. 5A shows FIG.
(N) is a plan view. By transferring the solder 48, a solder pump group 49G arranged in a matrix is formed.

In step 6), a resin spacer is formed.
In this embodiment, the resin for the resin spacer is DMD
50 parts by weight of a 50% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku: molecular weight 2500) dissolved in G (dimethyl glycol dimethyl ether), 50 parts by weight of a bisphenol A type epoxy resin, an imidazole curing agent (manufactured by Shikoku Chemicals) : Trade name 2E4MZ-CN) 4
A composition comprising 5 parts by weight of benzophenone as a photoinitiator (manufactured by Kanto Kagaku) was prepared.

Since the solder balls 48 are not formed in the via holes 44z located at the four corners in the solder bump group, the resin (uncured) for the above-mentioned composition is applied to the via holes 44z at the four corners. Inject and fill with a dispenser, and expose with an ultra-high pressure mercury lamp at 1000 mj / cm ² (FIG. 3 (O)). FIG. 5B is a plan view of FIG. In the present embodiment, the resin is cured by heating, exposed or exposed, and then heat-treated to form the resin spacer 50. Here, since the via hole 44z is filled, the resin does not flow and the spherical resin spacer 50 can be obtained by the surface tension of the resin.

Since the via hole 44 is made of metal, it can be easily recognized optically even when it is automatically injected with a dispenser or the like, and can be used instead of a target mark.

Next, as shown in FIG. 4 (P), the resin spacer 50 is heated and pressurized at 150 ° C. by using the flat plate 54 to be cured, and the height is adjusted to 60 μm. That is, these resins are left uncured, heated and pressed using a flat plate 54 to flatten the surface (fluttering), and then completely cured to form resin spacers. By flattening, when the IC chip is mounted, inclination is eliminated, and connection reliability can be improved.

As another method, there is a method in which an uncured resin is formed between solder bumps by screen printing, and this is cured by heating. Further, it is also possible to print a resin on the unformed area and harden the resin without forming the solder bump on a specific row of the solder bumps.

Further, when a semi-cured resin or a thermoplastic resin is used, the mounting position of the IC chip can be determined, and then the height can be adjusted by heating and pressing to fix the IC chip. Preferably, the resin spacer is a resin in a semi-cured state. This is because when mounting a semiconductor component such as an IC chip, it can be adjusted to an appropriate height by applying heat and pressure.

Next, as shown in FIG.
n = 9 / Pb = 1) Solder bump 64 made of solder 62
The IC chip 60 on which the semiconductor package 10 is formed
Is heated at 230 ° C. and pressurized to harden the resin spacer 50, and the solder 62 on the IC chip 60 and the solder 48 on the semiconductor package 10 are melted. Solder bump 64 on chip 60 side
And the solder bump 49 on the semiconductor package 10 side are electrically connected. FIG. 6 shows a partially enlarged view of the connection portion shown in FIG.

The distance between the surface of the semiconductor package 10 and the IC chip 60 is set to 50 to 1 by the resin spacer 50.
It is desirable to adjust it to 00 μm. That is, the interval is 5
If it is less than 0 μm, the height of the solder is too small, and there is no effect of preventing cracks. On the other hand, if the interval exceeds 100 μm, the fixing strength of the solder decreases, and the IC chip is easily detached.

The IC chip 60 and the semiconductor package 1
Solvent is injected into a connection portion with the solder 0, and the flux oozing out of the solders 62 and 48 is washed. Then, as shown in FIG. 4 (R), a silicone resin 70 is applied to the connection portion by using a capillary phenomenon. After that, it was thermally cured at 150 ° C. to seal the connection site. Thus, the semiconductor device is completed.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 7A is a plan view of a solder bump group 149G of the semiconductor package 110 according to the second embodiment, and FIG.
FIG. 3 is a cross-sectional view showing a state where an IC chip 60 is attached to the device. The configuration of the semiconductor package 110 of the second embodiment is as follows.
Although substantially the same as the first embodiment, as shown in FIG. 7A, a rectangular resin spacer 150 is formed by screen printing in a row orthogonal to each other in the solder bump group 149G.

The heat cycle characteristics of the semiconductor package 10 of the first embodiment, the semiconductor package 110 of the second embodiment, and the semiconductor package 210 having no resin spacer according to the prior art described above with reference to FIG. 8 were examined. FIG. 9 shows the results. Here, the thermal shock is -125.
A heat cycle at a temperature of 65 ° C. to 65 ° C. was repeated 1000 times to determine whether a crack occurred in the conductive circuit and the filled resin 26.

As shown in FIG. 9, the semiconductor package 10 of the first embodiment and the semiconductor package 1 of the second embodiment
In No. 10, since the height of the solder could be kept at a certain level or more by the resin spacer, cracks did not occur in the conductive circuit and the filling resin. On the other hand, in the semiconductor package 210 of the related art, cracks occurred in the above test.

In the first and second embodiments, the IC
Since the distance between the chip and the semiconductor package is kept at a certain value or more, the flux cleaning by injecting the solvent into the connection portion described above with reference to FIG.
As shown in (1), there is also an advantage that resin sealing can be easily performed by injecting silicone resin into the connection site.

In the first embodiment, the resin spacers 50 are arranged at the four corners of the solder bump group 49G. However, the resin spacers 50 are arranged at three or more places so that the space between the IC chip 60 and the semiconductor package 10 can be increased. Can be properly maintained.

[0053]

As described above, the semiconductor package and the semiconductor device of the present invention can maintain the height of the solder at a certain level or more by the resin spacer, so that the semiconductor package and the semiconductor device have excellent thermal shock resistance,
Excellent reliability.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor package according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor package according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor package according to the first embodiment of the present invention;

FIG. 5A is a plan view of FIG. 3M, and FIG.
FIG. 3B is a plan view of FIG.

FIG. 6 is an enlarged view of a connection site of the IC chip shown in FIG.

FIG. 7A is a plan view of a solder bump group when a resin spacer is provided in a via hole according to a second embodiment of the present invention, and FIG. 7B is a plan view of the solder bump group. To IC
It is sectional drawing of the semiconductor package in which the chip was mounted.

FIG. 8 is an enlarged view of a connection portion between an IC chip and a semiconductor package according to the related art.

FIG. 9 is a table showing the results of testing the heat cycle characteristics of the semiconductor packages of the first embodiment and the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor package 20 Substrate 44 Via hole 48 Solder 49 Solder bump 49G Solder bump group 50 Resin spacer 60 IC chip 62 Solder 64 Solder bump

Claims (6)

[Claims] 1. A semiconductor package in which a solder bump group for mounting a semiconductor component is formed on a wiring board, wherein the solder bump is formed by providing a solder body on a connection pad made of a metal conductor, A semiconductor package characterized by providing a resin spacer for ensuring a space between a semiconductor component and a connection pad in a region of the solder bump group. 2. The semiconductor package according to claim 1, wherein at least a part of the connection pad is formed as a via hole, and a resin is filled in a recess of the via hole to form a resin spacer. 3. The semiconductor package according to claim 1, wherein a resin spacer is formed between the solder bumps forming the solder bump group. 4. The semiconductor package according to claim 1, wherein said resin spacer is a resin in a semi-cured state. 5. The resin spacer is an epoxy resin, a polyimide resin, an epoxy-PES composite resin, an epoxy acrylate resin, or an epoxy-epoxy acrylate resin. The semiconductor package according to claim 1, wherein the semiconductor package is at least one selected from a silicone resin and a thermoplastic resin. 6. The semiconductor package according to claim 1, wherein a semiconductor component is electrically connected to the semiconductor package via a solder bump.
A semiconductor device wherein the distance between the semiconductor package surface and the semiconductor component is adjusted to 50 to 100 μm by a resin spacer.