JPH10207687A - First in first out memory device - Google Patents

Abstract

(57) [Summary] If a threshold used when outputting a flag indicating the amount of data is fixed, flexibility in design is lost. Therefore, the threshold can be changed. A FIFO memory performs writing and reading of data on a first-in first-out basis. The write address holding unit 4 performs FIFO based on a write signal to the FIFO memory 2.
The write address of the O memory 2 is obtained and held. The read address holding unit 6 obtains and holds a read address of the FIFO memory 2 based on a read signal to the FIFO memory 2. The data amount calculator 7 calculates the amount of data in the FIFO memory 2 based on the write address and the read address. The comparing unit 8 compares the amount of data in the FIFO memory 2 with a threshold value input from the outside, and outputs the comparison result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out memory device for reading data written first.

[0002]

2. Description of the Related Art In a first-in, first-out memory device for reading out previously stored data first, the amount of stored valid data is represented by using flags such as FULL, HALFFULL, and EMPTY. Peripheral devices of the first-in first-out memory device use this flag to determine the timing of writing and reading data. Here, FULL indicates that the effective data amount in the memory matches the memory capacity. HALF
FULL indicates that the effective data amount in the memory is half the memory capacity. EMPTY indicates that the amount of valid data in the memory is zero. In addition, with its extension ALMOSTFULL
And a flag such as ALMOSTEMPTY. Here, ALMOSTFULL indicates that the relationship of memory capacity> effective data amount in memory> (memory capacity−threshold) holds, and ALMOSTEMPTY indicates that the relationship of threshold> effective data amount in memory> 0 holds. Is shown.

[0003] If the threshold value is fixed, the design flexibility is lost. For example, a memory system disclosed in Japanese Patent Application Laid-Open No. 6-110653 and a device capable of changing the threshold value using a memory control method using the memory system are disclosed. And methods have been developed. In the memory system disclosed in Japanese Patent Laid-Open No. 6-110653, an arbitrary threshold value is stored in a register 22 as shown in FIG. 4, and a read address stored by an output counter 6a and a write address stored by an input counter 4a are stored. The amount of data stored in the dual port RAM 1c is calculated from the difference, and the flag is obtained by comparing the calculated amount of data with the threshold value stored in the register 22.

[0004]

However, the memory system disclosed in Japanese Patent Application Laid-Open No. 6-110653 requires a register for storing a threshold value, so that the circuit scale is large.

In particular, a plurality of registers are required to obtain each of the flags indicating the amount of valid data, which further increases the circuit size.

SUMMARY OF THE INVENTION The present invention has been made to solve such a disadvantage, and has as its object to provide a first-in first-out memory device in which a threshold can be freely changed without increasing the circuit scale.

[0007]

A first-in first-out memory device according to the present invention has a first-in first-out memory, a write address holding unit, a read address holding unit, a data amount calculation unit, and a comparison unit, and the first-in first-out memory has a write address and a read address. The write address holding unit is a unit for holding the write address of the first-in, first-out memory based on the first-in first-out memory, and updates the held write address based on the write signal to the first-in-first-out memory; Is the part that holds the read address of the first-in first-out memory,
The held read address is updated based on the read signal for the first-in first-out memory, and the data amount calculating unit calculates the data amount in the first-in first-out memory based on the write address held in the write address holding unit and the read address held in the read address holding unit. The comparison unit compares the data amount in the first-in first-out memory calculated by the data amount calculation unit with a threshold value input from the outside, outputs the comparison result, and inputs a threshold value of an arbitrary value when necessary. Then, the data storage state of the first-in first-out memory can be output.

The first-in first-out memory device has a first-in first-out memory, a write address holding unit, a data amount holding unit, a read address calculation unit, and a comparison unit. The first-in first-out memory writes data in a first-in first-out manner based on a write address and a read address. The write address holding unit is a unit for holding the write address of the first-in first-out memory, updates the held write address based on a write signal to the first-in-first-out memory, and the data amount holding unit stores the data amount stored in the first-in-first-out memory. Is a part that holds a value indicating the amount of data held, based on a write signal to the first-in first-out memory and a read signal to the first-in-first-out memory, and the read address calculation unit uses the write address held in the write address holding unit and De The read address of the first-in first-out memory is calculated based on the value indicating the data amount of the first-in first-out memory held by the data amount holding unit, and the comparison unit calculates the data amount in the first-in first-out memory held by the data amount holding unit and a threshold value input from the outside. And outputs the result of the comparison.

The first-in first-out memory device has a first-in first-out memory, a read address holding unit, a data amount holding unit, a write address calculating unit, and a comparing unit. The first-in first-out memory writes data in a first-in first-out manner based on a write address and a read address. The read address holding unit is a unit for holding the read address of the first-in first-out memory, updates the held read address based on a read signal for the first-in first-out memory, and the data amount holding unit updates the data amount stored in the first-in first-out memory. Is a part that holds a value representing the amount of data held, based on a write signal to the first-in first-out memory and a read signal to the first-in-first-out memory, and the write address calculation unit reads the read address held by the read address holding unit. De The write address of the first-in first-out memory is calculated based on the value indicating the data amount of the first-in first-out memory held by the data amount holding unit, and the comparison unit calculates the data amount in the first-in first-out memory held by the data amount holding unit and a threshold value input from the outside. And outputs the result of the comparison.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first-in first-out memory device according to the present invention writes and reads data in a first-in first-out manner, and indicates FULL, ALMOSTFULL, HALFFULL, and ALMOSTEMPTY representing the relationship between storage capacity and actual data storage capacity.
And a result corresponding to a flag such as EMPTY.

The first-in first-out memory device is, for example, a first-in first-out memory (hereinafter, referred to as a “FIFO memory”).
Input control circuit, write address holding unit, output control circuit,
It has a read address holding unit, a data amount calculation unit, and a comparison unit. The FIFO memory writes and reads data on a first-in first-out basis in accordance with the control of the input control circuit and the output control circuit, and the write address held by the write address holding unit and the read address held by the read address holding unit. The input control circuit outputs a write signal to the FIFO memory based on the external write signal,
It controls writing of data to the FO memory. The write address holding unit is a unit that holds the write address of the FIFO memory, and updates the held write address of the FIFO memory when receiving a write signal to the FIFO memory from the input control circuit. Here, the write address is an address indicating a data write destination of the FIFO memory. The output control circuit outputs a read signal to the FIFO memory based on an external read signal, and outputs the read signal to the FIFO memory.
Controls reading of data from memory. The read address holding unit holds the read address of the FIFO memory, and updates the held read address of the FIFO memory based on a read signal from the output control circuit to the FIFO memory. Here, the read address is FI
This is a data read address of the FO memory.

The data amount calculation unit calculates the data amount in the FIFO memory based on the write address stored in the write address storage unit and the read address stored in the read address storage unit. The comparison unit is the FI calculated by the data amount calculation unit.
The value indicating the amount of data in the FO memory is compared with an externally input threshold value, and the comparison result is output. If the peripheral device of the first-in first-out memory device needs information indicating the relationship between the storage capacity of the first-in-first-out memory device and the actual data storage amount, a threshold value is input from the peripheral device, and the comparing unit is adjusted in accordance with the timing. Read the comparison result from.
As described above, since an arbitrary threshold value can be input, various comparison results can be obtained according to the processing units of peripheral devices and the like. Further, since it is not necessary to store the threshold value in the first-in first-out memory device, it is possible to prevent an increase in circuit scale.

The first-in first-out memory device is a FIFO
An O memory, an input control circuit, a write address holding unit, an output control circuit, a data amount holding unit, a read address calculation unit, and a comparison unit may be provided. The data amount holding unit obtains and holds the data amount in the FIFO based on a write signal to the FIFO memory from the input control circuit and a read signal to the FIFO memory from the output control circuit. The read address calculation unit calculates the read address of the FIFO memory from the write address held by the write address holding unit and the value indicating the amount of data in the FIFO memory held by the data amount holding unit. The comparing section compares the value indicating the data amount in the FIFO memory held by the data amount holding section with the threshold value input by the threshold value input section, and outputs the comparison result.

The first-in first-out memory device is a FIFO
An O memory, an input control circuit, an output control circuit, a read address holding unit, a data amount holding unit, a write address calculation unit, and a comparison unit may be provided. The write address calculation unit calculates the write address of the FIFO memory from the read address held by the read address holding unit and the value indicating the amount of data in the FIFO memory held by the data amount holding unit.

[0015]

FIG. 1 is a block diagram of a first-in first-out memory device 1 according to one embodiment of the present invention. As shown in the figure, the first-in first-out memory device 1 includes a FIFO memory 2, an input control circuit 3, a write address holding unit 4, an output control circuit 5, a read address holding unit 6, a data amount calculation unit 7, and a comparison unit 8. In response to a write signal from the input control circuit 3 and a read signal from the output control circuit 5, the FIFO memory 2 writes data to the write address held by the write address holding unit 4 and reads data from the read address held by the read address holding unit 6. , And the data is written and read out on a first-in first-out basis. The input control circuit 3 outputs a write signal to the FIFO memory 2 in response to an external write signal, and controls writing of data to the FIFO memory 2. The write address holding unit 4 is a unit that holds a write address of the FIFO memory 2 and, for example, receives a write signal from the input control circuit 3 and, after the FIFO memory 2 writes data, increments the held write address. Here, when the write address reaches the upper limit address of the storage area of the FIFO memory 2, the write address holding unit 4 calculates the continuation from the start address of the storage area of the FIFO memory 2. The output control circuit 5 outputs a read signal to the FIFO memory 2 in response to an external read signal, and controls reading of data from the FIFO memory 2. The read address holding unit 6 is a FIFO memory 2
The read address is, for example, received from the output control circuit 5, and after reading data from the FIFO memory 2, the held read address is incremented. Here, the read address is F
When the upper limit address of the storage area of the IFO memory 2 is reached, the same processing as in the case of the write address is performed.

The data amount calculation unit 7 stores the write address stored in the write address storage unit 4 and the read address storage unit 6.
The valid data amount in the FIFO memory 2 is calculated based on the read address held in the step (1). For example, when data is stored from the smaller address of the FIFO memory 2 and the write address is larger than the read address, the data amount calculator 7 subtracts the read address from the write address to obtain the data amount, and Is smaller than the read address, the amount of data stored in the FIFO memory 2 is obtained by adding the value obtained by subtracting the read address from the last address of the FIFO memory 2 and the value obtained by subtracting the start address of the FIFO memory 2 from the write address.

The comparing unit 8 calculates the F calculated by the data amount calculating unit 7.
The data amount in the IFO memory 2 is compared with a threshold value input from a peripheral device (not shown), and the comparison result is output.
Here, the comparison result of the comparison unit 8 indicates that the value indicating the data amount in the FIFO memory 2 is larger than the threshold value, the value indicating the data amount in the FIFO memory 2 is equal to the threshold value, There are three cases where the value indicating the amount of data in the FIFO memory 2 indicates that the value is smaller than the threshold value.
Therefore, for example, if the threshold is set to a value close to the capacity of the FIFO memory 2 within a range smaller than the capacity of the FIFO memory 2, the same result as the flag of the ALMOSTFULL can be obtained.
If the threshold value is set to a value close to zero, a result similar to that of the ALMOSTEMPTY flag can be obtained. Similarly, by changing the threshold value, a result similar to the FULL, HALFFULL, and EMPTY flags can be obtained.

When a peripheral device needs the comparison result, a threshold value is input from the peripheral device to the comparison unit 8, and the comparison result from the comparison unit 8 is read in time with the input of the threshold value. I do. As described above, by inputting the threshold value when the comparison result is read by the peripheral device, it is not necessary to store the threshold value, and the circuit scale can be reduced. Also, since an arbitrary threshold can be input, an optimum comparison result can be obtained according to the number of bits constituting a word of a peripheral device.

As shown in FIG. 2, the first-in first-out memory device 1a comprises a FIFO memory 2, an input control circuit 3, a write address holding unit 4, an output control circuit 5, a data amount holding unit 9, a read address calculation unit 10, and a comparison unit. A section 8 may be provided. The data amount holding unit 9 is a unit for holding a value indicating the data amount in the FIFO memory 2, and upon receiving a write signal to the FIFO memory 2 from the input control circuit 3, increments the value indicating the held data amount and outputs the value. When a read signal from the control circuit 5 to the FIFO memory 2 is received, the value indicating the held data amount is decremented. The read address calculator 10 calculates a read address of the FIFO memory 2 from the write address held by the write address holder 4 and a value indicating the amount of data in the FIFO memory 2 held by the data amount holder 9. Therefore, the read address of the data from the FIFO memory 2 can be obtained without holding the read address. The comparison unit 8 compares the value indicating the data amount in the FIFO memory 2 held by the data amount holding unit 9 with a threshold value input from the outside, and outputs the comparison result as described above.

As shown in FIG. 3, the first-in first-out memory device 1b includes a FIFO memory 2, an input control circuit 3, an output control circuit 5, a read address holding unit 6, a data amount holding unit 9, a write address calculation unit 11, and a comparison unit. A section 8 may be provided. The write address calculation unit 11 calculates the write address of the FIFO memory 2 from the read address held by the read address holding unit 6 and the value indicating the amount of data in the FIFO memory 2 held by the data amount holding unit 9. Therefore, even if the write address is not held,
The address at which data is written to the O memory 2 can be obtained.

[0021]

As described above, the present invention holds a write address and a read address of data, calculates an amount of data based on the held write address and read address, and sets a value indicating the calculated data amount. Is compared with a threshold value input from the outside, and the comparison result is output. Therefore, when necessary, a threshold value of an arbitrary value can be input to output a data storage state.

Furthermore, since an arbitrary threshold value can be input, the threshold value can be freely selected in accordance with the data processing unit of the peripheral device, and the degree of freedom in peripheral design can be increased.

Further, since no threshold value is stored, a threshold value storage circuit is not required, and the device configuration can be reduced.

Further, the write address and a value indicating the data amount are held, and the read address is calculated based on the held write address and the value indicating the data amount, and a first-in first-out operation is performed according to the held write address and the calculated read address. Performs writing and reading of data, compares the value indicating the amount of data held with an externally input threshold value, and outputs the comparison result, so if there is no need to hold a read address, The data storage state can be output by inputting an arbitrary threshold value.

Also, a read address and a value indicating a data amount are held, a write address is calculated based on the held read address and a value indicating the data amount, and a first-in first-out operation is performed according to the calculated write address and the held read address. Write and read data, compare the value indicating the amount of data held with a threshold value input from the outside, and output the comparison result, so if it is necessary to have no means for holding the write address, The data storage state can be output by inputting an arbitrary threshold value.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a first-in first-out memory device including a read address calculation unit;

FIG. 3 is a configuration diagram of a first-in first-out memory device including a write address calculation unit;

FIG. 4 is a configuration diagram of a conventional memory system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 First-in first-out memory device 2 FIFO memory 3 Input control circuit 4 Write address holding part 5 Output control circuit 6 Read address holding part 7 Data amount calculation part 8 Comparison part 9 Data amount holding part 10 Read address calculation part 11 Write address calculation part

Claims (3)

[Claims] A first-in first-out memory, a write address holding unit, a read address holding unit, a data amount calculation unit, and a comparison unit, wherein the first-in first-out memory writes and reads data on a first-in first-out basis based on a write address and a read address; The write address holding unit is a unit that holds the write address of the first-in first-out memory, updates the held write address based on a write signal to the first-in-first-out memory, and the read address holding unit is a unit that holds the read address of the first-in-first-out memory, The held read address is updated based on the read signal for the first-in first-out memory, and the data amount calculating unit calculates the data amount in the first-in first-out memory based on the write address held in the write address holding unit and the read address held in the read address holding unit. Is calculated A first-in first-out memory device, wherein the comparison unit compares a value indicating the data amount in the first-in first-out memory calculated by the data amount calculation unit with a threshold value input from the outside, and outputs the comparison result. 2. A first-in first-out memory, a write address holding unit, a data amount holding unit, a read address calculating unit, and a comparing unit. The first-in first-out memory writes and reads data on a first-in first-out basis based on a write address and a read address. The write address holding unit is a unit that holds the write address of the first-in first-out memory, updates the held write address based on a write signal to the first-in-first-out memory, and the data amount holding unit holds a value that indicates the amount of data stored in the first-in-first-out memory Part to do
The value representing the amount of data held is updated based on the write signal to the first-in first-out memory and the read signal to the first-in-first-out memory, and the read address calculation unit writes the write address held in the write address holding unit and the first-in first-out memory held in the data amount holding unit A read address of the first-in first-out memory is calculated based on the value indicating the data amount, and the comparing unit compares the value indicating the data amount in the first-in first-out memory held by the data amount holding unit with a threshold value input from the outside,
A first-in, first-out memory device for outputting the comparison result. 3. A first-in first-out memory, a read address holding unit, a data amount holding unit, a write address calculating unit, and a comparing unit. The first-in first-out memory writes and reads data on a first-in first-out basis based on the write address and the read address. The read address holding unit is a unit that holds the read address of the first-in first-out memory, updates the held read address based on a read signal to the first-in-first-out memory, and the data amount holding unit holds a value that indicates the amount of data stored in the first-in-first-out memory Part to do
The value representing the held data amount is updated based on the write signal to the first-in first-out memory and the read signal to the first-in-first-out memory, and the write address calculation unit reads the read address held in the read address holding unit and the first-in first-out memory held in the data amount holding unit. The write address of the first-in first-out memory is calculated based on the value indicating the data amount, and the comparing unit compares the value indicating the data amount in the first-in first-out memory held by the data amount holding unit with a threshold value input from the outside,
A first-in, first-out memory device for outputting the comparison result.