JPH10313112A - Method for manufacturing semiconductor device - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of forming an electron beam resist (resist pattern) having a reverse tapered fine opening and forming a fine gate length pattern with high reliability. I will provide a. An subjected to electron beam exposure to the electron beam resist 4, 5 of the two layers, then by developing the second electron beam resist 5, which in the first opening 6 having a predetermined opening width w ₁ It is formed and then, through the first opening 6 by developing the first electron beam resist 4, forming the first major second opening 7 of the opening width w ₂ from the opening 6 . Thereafter, a recess groove 8 is formed in the semiconductor substrate 20 using the resists 5 and 4 in which the two openings 6 and 7 are formed as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a HEMT (High El
The present invention relates to a method for manufacturing a semiconductor device used in a step of forming a gate electrode of an ectron mobility transistor (high electron mobility transistor).

[0002]

2. Description of the Related Art Generally, in a HEMT, it is required to shorten a gate length of a gate electrode in order to increase a cutoff frequency and reduce a noise figure. Due to this requirement, electron beam exposure capable of forming a fine pattern is generally used for forming a gate electrode of a HEMT.

[0003] Here, HEMT (High Electron M
obility Transistor: a high electron mobility transistor is an n-type semiconductor having a small electron affinity (for example, n-AlGaAs).
s) and a high-purity semiconductor with a high electron affinity (for example, undoped GaAs) when joining (heterojunction)
FET operation is performed by using electrons (two-dimensional electron gas) with very high mobility that accumulate at the energy level lower than the Fermi level (at the high-purity semiconductor side) at the discontinuity of the band generated at the bottom of the conductor. Transistor.

FIGS. 3 (a) to 3 (c) and FIGS. 4 (d) to 4 (f)
FIG. 4 is a diagram for explaining a conventional forming process for forming a gate electrode of an EMT. First, as shown in FIG. 3A, a GaAs layer serving as a channel layer, an AlGaAs layer 2 serving as a secondary electron supply layer, and a high-concentration GaAs layer 3 serving as ohmic contact layers for source and drain are sequentially formed. A positive type electron beam resist 4 is applied on the HEMT substrate thus baked.

Next, in order to open a gate forming portion,
As shown in FIG. 3B, an electron beam exposure BM is performed on a portion corresponding to the gate formation region. Thus, only a portion of the electron beam resist 4 corresponding to the gate forming region is exposed. Next, as shown in FIG. 3C, development, washing, and drying are performed, and an opening 6 is formed in a portion of the electron beam resist 4 corresponding to the gate forming region.

Next, as shown in FIG. 4D, recess etching is performed on the substrate (high-concentration GaAs layer 3) using the electron beam resist 4 (that is, the resist pattern) in which the opening 6 is formed as a mask. 8 is formed.

Next, as shown in FIG. 4E, a metal wiring layer 10 for a gate electrode is deposited on the entire substrate. As a result, the metal wiring layer 10 is located on the bottom 9 of the recess groove 8 (FIG. 4).
In the example of (e), the AlG exposed by the recess groove 8 is formed.
(on the aAs layer 2) and the electron beam resist 4.

Thereafter, as shown in FIG. 4 (f), the electron beam resist 4 and the metal on the electron beam resist 4 are left except for the metal wiring layer 10 deposited on the bottom 9 of the recess groove 8 in the metal wiring layer 10. The wiring layer 10 is removed by a lift-off method. Thus, a semiconductor device in which the metal wiring layer 10 as the gate electrode is formed can be manufactured.

[0009]

By the way, in the above-mentioned method of manufacturing a semiconductor device, the literature "Modern GaAs Processi
ng Methods; Palph Williams p143-p14
As described in “5”, for example, in the process shown in FIGS. 3B and 3C, when an attempt is made to form a fine opening 6 of about 0.3 μm or less in the electron beam resist 4, the exposure of the electron beam exposure is performed. Even if the conditions and the development conditions are adjusted, the pattern (resist pattern) of the opening 6 of the electron beam resist 4 does not have a reverse tapered shape as shown in FIG. 3C (that is, a reverse tapered shape as shown in FIG. 5). The resist 4 (resist pattern) in which the opening 6 is formed in the recess etching step (step of FIG. 4D) for forming the recess groove 8 following the electron beam exposure. Is damaged by the etchant and the film is reduced, and the shape of the opening 6 becomes a forward taper.
(For example, a forward tapered pattern as shown in FIG. 6), the final lift-off step of the above manufacturing process (FIG. 4F)
In the step (2), the metal wiring layer 10 formed on the bottom 9 of the recess groove 8 is easily removed together with the unnecessary metal, and there is a problem that the production yield is very poor.

That is, for example, the opening diameter is about 0.3 μm
In the case where a fine gate length pattern of about 0.3 μm or less is to be formed by forming the following fine opening 6, the metal wiring layer 10 formed in the bottom 9 of the recess groove 8 is formed by the above-described conventional manufacturing method. Is also easily removed, and the production yield is very poor.

The present invention provides a method of manufacturing a semiconductor device capable of forming an electron beam resist (resist pattern) having an inverse tapered fine opening and forming a fine gate length pattern with high reliability. It is intended to be.

[0012]

In order to achieve the above object, according to the first aspect of the present invention, a first electron beam resist is applied on a semiconductor substrate and baked, and further a second electron beam resist is applied thereon. Applying an electron beam resist and baking; performing an electron beam exposure on the first and second electron beam resists; and developing the second electron beam resist to form the second electron beam resist. Forming a first opening having a predetermined opening width in the electron beam resist; developing the first electron beam resist through the first opening to develop a first opening having a larger opening width than the first opening; Forming a second opening in the first electron beam resist; and forming a recess in the semiconductor substrate using the first and second electron beam resists in which the first and second openings are respectively formed as a mask. Forming, depositing a metal wiring layer for a gate electrode over the entire surface of the semiconductor substrate, and leaving the first and second electron beams while leaving the metal wiring layer of the metal wiring layer deposited in the recess groove. Removing the resist and unnecessary metal wiring layers thereon by a lift-off method.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, at least an organic developer is used for developing the second electron beam resist, and the first electron beam resist is developed. It is characterized in that at least an alkaline developer is used for development.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the thickness of the metal wiring layer for the gate electrode is made at least equal to or less than the thickness of the first electron beam resist. It is characterized by:

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (d), 2 (e) to 2 (e)
(h) is a diagram for explaining the method for manufacturing the semiconductor device according to the present invention. Referring to FIGS. 1A to 1D and 2E to 2H, first, a positive first electron beam resist 4 is formed on a semiconductor substrate 20 (for example, HEMT substrates 1, 2, 3). Is applied and baked (FIG. 1A), and a positive second electron beam resist 5 is applied thereon and baked (FIG. 1B).

Next, electron beam exposure BM is performed on the two layers of electron beam resists 4 and 5 (FIG. 1).
(c)). Then, the second electron beam resist 5 is developed with a predetermined developing solution (for example, an organic developing solution) to form a first opening 6 having a predetermined opening width (opening diameter) w ₁ in the second electron beam resist 5. It is formed (FIG. 1D). Next, the first electron beam resist 4 is passed through the first opening 6 with a predetermined developing solution.
(For example, an alkali developing solution), and the first opening 6
Forming a large second opening 7 of the opening width (opening diameter) w ₂ than (Fig. 2 (e)).

Thereafter, a recess groove 8 is formed in the semiconductor substrate 20 (HEMT substrate) using the resists 5 and 4 (resist pattern) in which the two openings 6 and 7 are formed as a mask (FIG. 2F). ). Thereafter, a metal wiring layer 10 for a gate electrode is deposited on the entire surface of the substrate (FIG. 2G). At this time, the thickness of the metal wiring layer for the gate electrode should be at least the first.
The thickness is preferably equal to or less than the thickness of the electron beam resist. That is, by making the thickness of the metal wiring layer for the gate electrode smaller than the thickness of the first electron beam resist, the recess groove 8 is formed.
Since a gap is formed between the upper gate electrode and the upper layer of the second electron beam resist, it is difficult to remove the unnecessary metal together with the unnecessary metal in the lift-off process.

Then, the first and second electron beam resists 4 and 5 and the unnecessary portions on the first and second electron beam resists 5 and 5 are left, leaving the metal wiring layer 10 deposited on the bottom (bottom) 9 of the recess groove 8 in the metal wiring layer 10. The unnecessary metal wiring layer 10 is removed by a lift-off method (FIG. 2 (h)). Thus, a semiconductor device in which the metal wiring layer 10 as the gate electrode is formed can be manufactured.

In the above-described manufacturing method of the present invention, the first resist 4 formed in the lower layer is smaller than the opening diameter w _{1 of} the first opening 6 formed in the second resist 5 which is the upper layer. The opening diameter w2 of the _second opening 7 is larger than the opening diameter w2. Therefore, the first opening 6 and the second opening 7 allow the opening 6 having a substantially reverse tapered shape as viewed from the upper layer. ,
It is possible to obtain a resist (resist pattern) in which 7 is formed (resist in which an opening substantially similar to that shown in FIG. 5 is formed).

In this case, in order to form a fine gate length pattern, the opening diameter w ₁ of the _first opening 6 and the second opening 7
When the opening diameter w ₂ of the first opening 6 and the second opening 7 is small (for example, about 0.3 μm or less), the opening pattern shape of the first opening 6 and the second opening 7 is such an inverted taper shape. Things. Therefore, at this time, even when the lift-off step shown in FIG. 2H is performed, the recesses 8 are formed by forming the inverse tapered fine openings 6 and 7 in the resists 4 and 5. The fine (for example, a gate length of about 0.3 μm or less) metal wiring layer 10 deposited on the bottom 9 of the substrate is hardly removed, and the manufacturing yield can be improved.

By making the thickness of the metal wiring layer for the gate electrode at least equal to or less than the thickness of the first electron beam resist, the gate electrode on the recess groove 8 and the second electron beam resist as the upper layer can be formed. Since there is a gap between them, it is difficult to remove them together with unnecessary metals in the lift-off step, and the production yield can be improved.

[0022]

Next, an embodiment of the present invention will be described.
First, as shown in FIG.
s layer, AlGaAs layer 2 serving as a secondary electron supply layer, high concentration G serving as an ohmic contact layer for source and drain
On the HEMT substrate 20 on which the aAs layer 3 is sequentially formed,
First electron beam resist 4, for example, Microlithography Chemical Corporation (MCC, USA)
PMGI-SF8 was applied to a thickness of about 4500 ° and baked at a temperature of 200 ° C. for 30 minutes in a nitrogen atmosphere. Next, as shown in FIG. 1B, a second electron beam resist 5, for example, ZEON manufactured by Zeon Corporation
P520-12 was applied to a thickness of about 3000 ° and baked at a temperature of 200 ° C. for 30 minutes in a nitrogen atmosphere.

Thereafter, an electron beam exposure BM is performed as shown in FIG. Next, as shown in FIG.
Layer of resist 4 was applied to an organic developer ZED- manufactured by Zeon Corporation.
Development was carried out at 50 N to form openings 6 in the first layer of resist 4. The development time at this time was about 3 minutes. Thereafter, rinsing is performed for about 1 minute with isopropyl alcohol, and then, as shown in FIG.
By developing with DW, an opening 7 was formed in the resist 5 of the second layer. The development time at this time was about 45 seconds.
Next, as shown in FIG. 2 (f), recess etching for forming a recess groove was performed with a citric acid-based etchant through the openings 6 and 7 to expose the AlGaAs layer 9 on the substrate surface. That is, the recess groove 8 is formed in the high-concentration GaAs layer 3.
Was formed.

Next, as shown in FIG. 2G, Ti / Au was deposited on the entire surface as a metal wiring layer 10 for forming a gate electrode to a thickness of about 3000 °. Thereafter, as shown in FIG. 2H, the lift-off was performed while leaving only the metal wiring layer 10 deposited on the bottom surface 9 of the recess groove 8.

According to the method of this embodiment, one electron beam exposure and a development process divided into two steps ensure that a fine (aperture diameter of 0.3 μm or less) having a reverse tapered shape is obtained.
The openings 6 and 7 can be formed in the resists 5 and 4, and the resist pattern in which the fine openings in the reverse taper shape are formed,
A gate electrode 10 having a fine (about 0.3 μm or less) gate length
Was formed with high reliability.

In the above embodiment, the semiconductor substrate 20
Is an AlGaAs / GaAs HEMT substrate, but the semiconductor substrate 20 may be an InAlAs / InGaAs HEMT substrate, or alternatively, an AlGaAs / I HEMT substrate.
The present invention can be applied in exactly the same manner to an HEMT substrate of nGaAsP, and the same effect can be obtained.
Further, when the semiconductor substrate 20 is a substrate other than the HEMT substrate,
For example, a GaAs-based MESFET substrate or an InP-based MES
The present invention can be applied to FETs and the like in exactly the same manner, and the same effects can be obtained.

In the above-described embodiment, PMGI-SF8 is used as the first electron beam resist 4 and ZEP520-12 is used as the second electron beam resist 5. However, as the first electron beam resist 4, for example, OEBR2000 manufactured by Tokyo Ohka Co., Ltd. or SAL-101 manufactured by Shipley Far East Co., Ltd. can also be used.
R1000 or EBR9 manufactured by Toray Co., Ltd. can also be used. In this case, the same effect as described above can be obtained.

[0028]

As described above, according to the first to third aspects of the present invention, a first electron beam resist is applied to a semiconductor substrate and baked, and further, a first electron beam resist is applied to the semiconductor substrate. Applying a second electron beam resist and baking; performing an electron beam exposure on the first and second electron beam resists; and developing the second electron beam resist to form the second electron beam resist. Forming a first opening having a predetermined opening width in the electron beam resist, and developing the first electron beam resist through the first opening to have a larger opening width than the first opening. Forming a second opening in the first electron beam resist; and forming a recess in the semiconductor substrate using the first and second electron beam resists in which the first and second openings are respectively formed as a mask. Forming, depositing a metal wiring layer for a gate electrode over the entire surface of the semiconductor substrate, and removing the first and second electron beams while leaving the metal wiring layer of the metal wiring layer deposited in the recess groove. Removing the resist and the unnecessary metal wiring layer thereon by a lift-off method, so that a resist pattern having a fine opening in a reverse taper shape can be formed, and the lift-off process of the fine gate electrode can be performed. The production yield can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram illustrating a conventional method of manufacturing a semiconductor device.

FIG. 4 is a diagram showing a conventional method for manufacturing a semiconductor device.

FIG. 5 is a diagram for explaining a reverse tapered opening pattern of an electron beam resist.

FIG. 6 is a diagram for explaining a forward tapered opening pattern of an electron beam resist.

[Explanation of symbols]

 Reference Signs List 1 GaAs layer 2 AlGaAs layer 3 High concentration GaAs layer 4 First electron beam resist 5 Second electron beam resist 6 Opening 7 Opening 8 Recessed groove 9 Recessed groove bottom 20 Semiconductor substrate

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/027 H01L 29/80 F 29/417

Claims (3)

[Claims] A step of applying a first electron beam resist on a semiconductor substrate to perform baking, and further applying a second electron beam resist thereon to perform baking; Performing an electron beam exposure on the electron beam resist, and developing the second electron beam resist to form a first opening having a predetermined opening width in the second electron beam resist; Developing the first electron beam resist through the first opening to form a second opening having a larger opening width in the first electron beam resist than the first opening; , Second opening formed with the first and second openings, respectively.
Forming a recess groove in a semiconductor substrate using the electron beam resist as a mask, depositing a metal wiring layer for a gate electrode over the entire surface of the semiconductor substrate, and forming a metal wiring layer deposited in the recess groove among the metal wiring layers. Removing the first and second electron beam resists and unnecessary metal wiring layers thereon by a lift-off method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein at least an organic developer is used for developing the second electron beam resist, and at least an alkali developer is used for developing the first electron beam resist. A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the metal wiring layer for the gate electrode is at least equal to or less than the thickness of the first electron beam resist. Production method.