JPH1031625A - マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ - Google Patents

マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ

Info

Publication number
JPH1031625A
JPH1031625A JP9036260A JP3626097A JPH1031625A JP H1031625 A JPH1031625 A JP H1031625A JP 9036260 A JP9036260 A JP 9036260A JP 3626097 A JP3626097 A JP 3626097A JP H1031625 A JPH1031625 A JP H1031625A
Authority
JP
Japan
Prior art keywords
copyback
data
controller
address
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9036260A
Other languages
English (en)
Japanese (ja)
Inventor
Bjorn O Liencres
オー リーンクレス ビヨルン
Ashok Singhal
シンガル アショク
David J Broniarczyk
ジェイ ブローニアークジーク ディヴィッド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of JPH1031625A publication Critical patent/JPH1031625A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP9036260A 1996-02-27 1997-02-20 マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ Pending JPH1031625A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/607364 1996-02-27
US08/607,364 US5765196A (en) 1996-02-27 1996-02-27 System and method for servicing copyback requests in a multiprocessor system with a shared memory

Publications (1)

Publication Number Publication Date
JPH1031625A true JPH1031625A (ja) 1998-02-03

Family

ID=24431961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9036260A Pending JPH1031625A (ja) 1996-02-27 1997-02-20 マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ

Country Status (3)

Country Link
US (1) US5765196A (de)
EP (1) EP0793178A3 (de)
JP (1) JPH1031625A (de)

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JPH09204403A (ja) * 1996-01-26 1997-08-05 Hitachi Ltd 並列計算機
US5946709A (en) * 1997-04-14 1999-08-31 International Business Machines Corporation Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing
KR19980081499A (ko) * 1997-04-17 1998-11-25 모리시다요이치 메모리 내장 데이터 처리장치 및 처리시스템
EP1454253A4 (de) * 1997-12-19 2010-12-29 Bull Hn Information Syst Verwaltung von cachespeicherfehlgriffen und zugriffen in einem mehrprozessorrechnersystem mit privaten cachespeichern für einzelne prozessoreinheiten und einengemeinsamen cachespreicher
US6347361B1 (en) * 1998-02-17 2002-02-12 International Business Machines Corporation Cache coherency protocols with posted operations
US6131113A (en) * 1998-02-24 2000-10-10 International Business Machines Corporation Managing a shared resource in a multi-processor system
US6466993B1 (en) * 1998-11-05 2002-10-15 Compaq Information Technologies Group, L.P. Method and apparatus for performing transactions rendering between host processors and I/O devices using concurrent non-blocking queuing techniques and I/O bus write operations
US6298417B1 (en) * 1998-11-20 2001-10-02 International Business Machines Corporation Pipelined cache memory deallocation and storeback
US6636950B1 (en) * 1998-12-17 2003-10-21 Massachusetts Institute Of Technology Computer architecture for shared memory access
US6725307B1 (en) * 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US6401175B1 (en) * 1999-10-01 2002-06-04 Sun Microsystems, Inc. Shared write buffer for use by multiple processor units
US6484238B1 (en) * 1999-12-20 2002-11-19 Hewlett-Packard Company Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache
SE522447C2 (sv) 2000-02-29 2004-02-10 System Edstroem Bilinredningar För uppbyggnad av lådhurtsar avsedd kassett av det slag som hyser en utdragslåda
US7363427B2 (en) * 2004-01-12 2008-04-22 Hewlett-Packard Development Company, L.P. Memory controller connection to RAM using buffer interface
US9270770B2 (en) * 2004-06-30 2016-02-23 Cisco Technology, Inc. System and method for optimizing publication of operating states
US7225300B1 (en) 2004-09-15 2007-05-29 Azul Systems, Inc Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
JP4366298B2 (ja) 2004-12-02 2009-11-18 富士通株式会社 記憶装置、その制御方法及びプログラム
JP2006185348A (ja) * 2004-12-28 2006-07-13 Fujitsu Ltd マルチプロセッサシステム及びロックフラグ操作方法
US8732409B2 (en) * 2008-11-17 2014-05-20 Entropic Communications, Inc. Cache management policy and corresponding device
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
RU2475822C1 (ru) * 2011-12-08 2013-02-20 Учреждение Российской академии наук Научно-исследовательский институт системных исследований РАН (НИИСИ РАН) Подсистема памяти ядра микропроцессора
RU2475817C1 (ru) * 2011-12-08 2013-02-20 Учреждение Российской академии наук Научно-исследовательский институт системных исследований РАН (НИИСИ РАН) Устройство буферизации потоков данных, считываемых из озу
JP2014182488A (ja) * 2013-03-18 2014-09-29 Fujitsu Ltd 演算処理装置、及び演算処理装置の制御方法
JP2018503156A (ja) * 2015-12-17 2018-02-01 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． 書込み要求処理方法、プロセッサおよびコンピュータ
CN120371729A (zh) * 2025-03-14 2025-07-25 北京算能科技有限公司 数据处理方法、缓存子系统及多处理器系统

Family Cites Families (6)

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EP0468831B1 (de) * 1990-06-29 1997-10-15 Digital Equipment Corporation Busprotokoll für Prozessor mit write-back cache
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5434993A (en) * 1992-11-09 1995-07-18 Sun Microsystems, Inc. Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
US5530933A (en) * 1994-02-24 1996-06-25 Hewlett-Packard Company Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
EP0735487B1 (de) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
US5581729A (en) * 1995-03-31 1996-12-03 Sun Microsystems, Inc. Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system

Also Published As

Publication number Publication date
US5765196A (en) 1998-06-09
EP0793178A3 (de) 1998-04-15
EP0793178A2 (de) 1997-09-03

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