JPH11214403A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control precisely a threshold voltage of a junction FET(Field-Effect Transistor), etc., by less suppressing impurity diffusion in a traverse direction by using impurity segregation by boron. SOLUTION: After forming an n-type conduction layer 16 on a p-type conduction layer on a surface of a GaAs board 12, a part of the n-type conduction layer is exposed from a photo resist film 20, and a p<+> -type conduction layer 22 is formed by jointly implanting an MG ion of 20 keV, 2×10<13> /cm<2> and B ion of 20 keV, 10<11> /cm<2> to the n-type conduction layer 16 through an opening 21 of the photo resist film 20. Next, an SiN film is formed on whole surface of the GaAs board 12 by CVD method, and the GaAs board 12 is capped and an activation heat treatment is conducted with 850 deg.C for 15 minutes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a junction semiconductor device such as a junction field effect transistor (junction FET or JFET) or a pn junction diode used in a high-frequency block of a mobile communication system, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As an impurity (p-type impurity) for forming a p-type conductive layer in a III-V group compound semiconductor such as GaAs, zinc (Zn), magnesium (M
g), beryllium (Be) or the like is used. For example, in a junction FET, these p-type impurities are doped at a high concentration into a n-type conductive layer by a thermal diffusion method or an ion implantation method to form ap ⁺ -type conductive layer in the n-type conductive layer, and a gate formation region is formed. A method of forming ap ⁺ -n junction is adopted.

FIG. 1 shows a case of a thermal diffusion method, in which a GaAs substrate 2 on which an n-type conductive layer 1 is formed is heat-treated in a Zn atmosphere, and Zn
FIG. 3 shows a state in which ap ⁺ -type conductive layer 6 is formed in the n-type conductive layer 1 by diffusing it into the n-type conductive layer 1.

[0004]

However, in general, p-type impurities such as Zn, Mg, and Be are GaAs.
Since the diffusion coefficient in the inside is large, the diffusion width of the impurity becomes considerably larger than the opening width of the mask. That is, when the GaAs substrate is kept at a high temperature after the implantation or diffusion of the p-type impurity,
The diffusion of the p-type impurity increases the diffusion depth of the p-type conductive layer, and the impurity also expands in the lateral direction (parallel to the substrate surface), thereby increasing the diffusion width. Further, since it is very difficult to control the diffusion width, it is also difficult to control the threshold voltage of a junction type FET or the like.

For this reason, conventionally, as a method for producing ap ⁺ -type conductive layer in a junction FET, only thermal diffusion by Zn has been practically used. But,
Even if the thermal diffusion method of Zn is used, the diffusion of Zn in the lateral direction is large, so that it was not practical if the width of the p ⁺ -type conductive layer had to be reduced. For example, when the gate length of the junction FET is reduced to less than 1 μm, it becomes difficult to form the junction FET even by using the thermal diffusion method of Zn.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and has as its object to reduce impurity diffusion in the lateral and depth directions by utilizing the segregation of impurities by boron. To keep it down.

[0007]

DISCLOSURE OF THE INVENTION A semiconductor device according to the present invention has a second conductive layer having a conductivity type different from that of the first conductive layer inside the first conductive layer.
Wherein the second conductive layer is doped with boron together with an impurity for imparting the conductive type to the second conductive layer. I have.

The inventor of the present invention has found that impurities (eg, Mg, etc.) are easily segregated on the surface of a semiconductor having a high boron concentration (eg, a compound semiconductor such as GaAs). In a semiconductor having a high boron concentration, impurities are easily segregated on the surface, which can suppress the diffusion of the impurities. Therefore, the diffusion of the impurities in the semiconductor in the lateral direction can be suppressed and the depth of the impurity can be reduced. Diffusion can also be suppressed. Therefore, diffusion of impurities in the lateral direction can be minimized, and a junction-type semiconductor device having a short gate length of, for example, 0.5 μm can be realized. At the same time, impurities segregate on the semiconductor surface, so that a thin high concentration layer can be realized by impurity implantation or the like. Therefore, an error between the diffusion width of the second conductive layer and the opening width of the mask pattern is small, a thin high-concentration layer can be manufactured, and the threshold voltage of a junction FET or the like can be precisely controlled. .

Here, as a method of adding boron to the semiconductor layer, a semiconductor substrate containing boron at a concentration of 5 × 10 ¹⁶ cm ⁻³ or more may be used, or boron may be co-implanted with impurities.

[0010]

2 (a) to 2 (d) and FIG.
(E) to (g) are junction type FEs according to an embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of T11. Hereinafter, a method of manufacturing the junction type FET 11 and a structure thereof will be described with reference to FIGS. First, a photoresist film 13 formed on the surface of a semi-insulating GaAs substrate 12 is opened in the element region, and Mg ions are introduced into the GaAs substrate 12 through the opening 14 of the photoresist film 13 at 350 keV, 4 × 10 ¹² / cm ^2.
To form a p-type conductive layer 15 (FIG. 2A). Then, Si ions are shallowly implanted into the p-type conductive layer 15 through the opening 14 at 120 keV and 8 × 10 ¹² / cm ² , An n-type conductive layer 16 is formed on the conductive layer 15 [FIG.
(B)]. In the source electrode formation region and the drain electrode formation region (both ends of the p-type conductive layer 15 and the n-type conductive layer 16), an opening 1 is formed by a photolithography technique in another photoresist 17 covering the surface of the GaAs substrate 12.
8 and the GaAs substrate 12 is
i ions are deeply implanted at 350 keV and 4 × 10 ¹³ / cm ² to form contact layers (n ^{+ type} conductive layers) 19 on both sides of the p type conductive layer 15 and the n type conductive layer 16 [FIG.
(C)].

Next, the surface of the GaAs substrate 12 is covered with a new photoresist film 20, and the photoresist film 20 is selectively opened in a gate formation region (the center of the n-type conductive layer 16). 20k in layer 16
eV, 2 × 10 ¹³ / cm ² Mg ions and 20 keV,
B ions of 1 × 10 ¹¹ / cm ² are co-implanted to form ap ⁺ -type conductive layer 22 [FIG. 2D]. After removing the photoresist film 20, an SiN film 25 is formed on the entire surface of the GaAs substrate 12 by the CVD method, the GaAs substrate 12 is capped with the SiN film 25, and activation heat treatment is performed at 850 ° C. for 15 minutes.

Next, the SiN film 25 is opened in the source electrode formation region and the drain electrode formation region by using the photolithography technique, and an AuGe-based metal is deposited on the contact layer 19 through the openings, and the lift-off method is used. The unnecessary portion of the metal is removed to remove the source electrode 23.
Then, an alloying heat treatment is performed at 440 ° C. in a nitrogen gas atmosphere to form the source electrode 23 and the drain electrode 24 into the contact layer 19 (FIG. 3E).
Ohmic junction.

Thereafter, an opening equal to the gate length is formed in the SiN film 25 on the p ^{+ type} conductive layer 22 by using the photolithography technique. Further, another photoresist film 26 is applied on the SiN film 25, and an opening slightly wider than the gate length is formed in the photoresist film 26. Then G
The aAs substrate 12 is set to H ₃ PO ₄ : H ₂ O ₂ : H ₂ O = 1: 1: 1.
After immersing in a liquid of 250 (volume ratio) for about 15 seconds, cleaning the surface of the p ⁺ -type conductive layer 22 through each opening of the photoresist film 26 and the SiN film 25, the lower layer side is formed on the p ⁺ -type conductive layer 22. Pt (film thickness 25 nm) / Mo (film thickness 2
0 nm) / Ti (film thickness 100 nm) / Au (film thickness 350)
(FIG. 3).
(F)], a mushroom type gate electrode 28 is formed by removing the upper photoresist film 26 [FIG. 3 (g)]. Thereafter, a heat treatment is performed at about 350 ° C. for 5 minutes to remove almost all of Pt under the gate electrode 28 from p.
Diffusion into the ^{+ type} conductive layer 22 to ensure ohmic contact with the p ^{+ type} conductive layer 22. Finally, form a wiring pattern layer,
By forming a protective film, the junction type FET 11 is completed.

Although Mg has a relatively low diffusion coefficient than Zn, the inventors of the present invention promoted surface segregation of Mg by co-implanting B ions with Mg ions, as in the above-described production method. It has been discovered that thermal diffusion on the substrate side can be suppressed. In particular, by setting the concentration of boron co-implanted with Mg ions to be 5 × 10 ¹⁶ / cm ³ or more,
It was found that the surface segregation of Mg was promoted.

The concentration of boron co-implanted with Mg is 1 × 1
FIG. 4 shows the measurement results of the relationship between the depth measured from the substrate surface and the atomic concentration of Mg in the cases of 0 ¹⁶ / cm ³ and 5 × 10 ¹⁷ / cm ³ . According to FIG. 4, when the boron concentration is 1 × 10 ¹⁶ / cm ³ , the Mg atom concentration is maximum at a depth of about 0.1 μm, but the co-implanted boron concentration is 5 × 10 ¹⁶ / cm ^{3. At 17} / cm ³ , the atomic concentration in the shallow region is high and the atomic concentration in the deep region is low, indicating that Mg is segregated on the surface.

Therefore, co-implantation of B ions with a concentration of 5 × 10 ¹⁶ / cm ³ or more together with Mg ions through the opening of the mask promotes Mg surface segregation and suppresses thermal diffusion. The shallow p ⁺ -type conductive layer 22
(Thin layer and high concentration p layer) are formed, a steep p ⁺ -n junction can be formed, and device characteristics and reliability can be improved. Further, the thermal diffusion of Mg in the lateral direction is also suppressed, and the diffusion width of the p ⁺ -type conductive layer 22 can be made substantially equal to the opening width of the mask, so that the junction FET 11 having a gate length of 0.5 μm can be realized.

FIG. 6 is a graph comparing the characteristics of a conventional junction FET and the junction FET according to the present invention. Curve A1 shows the drain current of the conventional junction FET, and curve B1 shows the junction FET of the present invention. The curve A2 shows the transconductance (gm) of the conventional junction FET, and the curve B2 shows the transconductance (gm) of the junction FET of the present invention.

When a p ⁺ -n junction is formed by Zn diffusion or a simple ion implantation method as in a conventional junction FET, p-type ions are transferred from the surface into the GaAs substrate during thermal diffusion or activation heat treatment. Therefore, an active layer having a high mutual inductance (high gm) could not be manufactured. On the other hand, in the present invention, by coexisting a certain amount of B with p-type ions such as Mg, a shallow high-concentration p ⁺ -type conductive layer can be realized on the contrary due to surface segregation at the time of heat treatment. It can be realized junction FET having a type p ⁺ -n junction. As a result, in the junction FET of the present invention, as shown in FIG.
High gm that is important for T can be realized, especially for power FET
It is effective in such as.

(Second Embodiment) In the first embodiment, B ions are co-implanted with Mg ions. However, even if B ions are preliminarily doped on a GaAs substrate, a similar process is performed in a junction FET. A shallow high-concentration p ⁺ -type conductive layer 22 can be realized. Hereinafter, the manufacturing process in this case will be briefly described with reference to FIGS.

First, by thermal diffusion or ion implantation, B
Mg ions are doped on the surface of the element region of the GaAs substrate 12 doped with ions at a concentration of 5 × 10 ¹⁶ / cm ³ or more.
At 50 keV, 4 × 10 ¹² / cm ^{2 is} implanted to form the p-type conductive layer 15, and then Si ions are implanted at 120 keV.
The n-type conductive layer 16 is formed on the p-type conductive layer 15 by implanting 8 × 10 ¹² / cm ² . Furthermore, Si ions were applied to the source electrode formation region and the drain electrode formation region (both ends of the p-type conductive layer 15 and the n-type conductive layer 16) at 350 keV and 4 × 1.
0 ¹³ / cm ² , the p-type conductive layer 15 and the n-type conductive layer 1
A contact layer (n ⁺ -type conductive layer) 19 is formed on both sides of FIG. 6 (FIG. 7A).

Next, the surface of the GaAs substrate 12 is covered with a photoresist film 20 to form a gate formation region (n-type conductive layer 16).
At the center), the photoresist film 20 is selectively opened, and through the opening 21 into the n-type conductive layer 16 at 20 keV.
Mg ions of 2 × 10 ¹³ / cm ² are implanted to form the p ⁺ -type conductive layer 22 [FIG. 7B]. After removing the photoresist film 20, the GaAs substrate 12 is capped with the SiN film 25, and an activation heat treatment is performed at a processing temperature of 850 ° C. for 15 minutes.

Next, Au-G is formed on the contact layer 19.
An e-based metal is deposited to form a source electrode 23 and a drain electrode 24 (FIG. 7C), and an alloying heat treatment is performed at 440 ° C. in a nitrogen gas atmosphere to convert the source electrode 23 and the drain electrode 24 to the contact layer 19. Ohmic junction.

Thereafter, the GaAs substrate 12 is placed on H ₃ PO ₄ : H
A solution of ₂ O ₂ : H ₂ O = 1: 1: 250 (volume ratio) takes about 15
After performing immersed in a surface cleaning of the p ⁺ type conductive layer 22 seconds, Pt (thickness 25 nm) on the p ⁺ type conductive layer 22 / M
o (film thickness 20 nm) / Ti (film thickness 100 nm) / Au
An electrode metal having a thickness of 350 nm is deposited to form the gate electrode 28 (FIG. 7D). Then, about 35
0 ℃ and was heat-treated for 5 minutes, the almost all the Pt of the gate electrode 28 lower is diffused into the p ⁺ type conductive layer 22, to ensure the ohmic property between the p ⁺ type conductive layer 22. Finally, a wiring pattern layer is formed, a protective film is formed, and the junction type FET is formed.
11 is completed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a process of forming a p ⁺ -type conductive layer in a conventional example.

FIGS. 2A to 2D are diagrams illustrating a manufacturing process of a junction FET according to an embodiment of the present invention.

3 (e) to 3 (g) are continuation diagrams of the above.

FIG. 4 is a diagram showing the relationship between the atomic concentration of Mg co-implanted with boron and the depth measured from the substrate surface.

FIG. 5 is a diagram showing a diffusion width of Mg co-implanted with B;

FIG. 6 shows a conventional junction FET and a junction FE according to the present invention.
FIG. 6 is a diagram comparing characteristics of T.

FIGS. 7A to 7D are diagrams illustrating a manufacturing process of a junction type FET according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 12 semi-insulating GaAs substrate 15 p-type conductive layer 16 n-type conductive layer 19 contact layer (n ⁺ -type conductive layer) 22 p ⁺ -type conductive layer 28 gate electrode

Claims (3)

[Claims] 1. A junction type semiconductor device in which a second conductive layer having a conductivity type different from that of the first conductive layer is formed inside a first conductive layer, wherein the second conductive layer comprises: A semiconductor device, wherein boron is added to a second conductive layer together with an impurity for imparting its conductivity type. 2. A method for producing a first conductive layer inside the first second junction type conductive layers are formed guide having a conductive layer different conductivity type electrically semiconductor device of a concentration 5 × 10 ¹⁶ After forming a first conductive layer by doping an impurity into a semiconductor substrate containing boron of cm ^-3 or more, a conductivity type different from the conductivity type of the first conductive layer is provided inside the first conductive layer. Forming a second conductive layer by doping impurities for forming the second conductive layer. 3. A method for manufacturing a junction-type semiconductor device in which a second conductive layer having a conductivity type different from that of the first conductive layer is formed inside the first conductive layer, wherein impurities are added to the semiconductor substrate. After doping to form a first conductive layer, an impurity for giving a conductivity type different from the conductivity type of the first conductive layer and boron are co-implanted into the first conductive layer to form a second conductive layer. A method for manufacturing a semiconductor device, comprising forming a layer.