JPH11304872A - Semiconductor device tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the measuring time and reduce production cost in a semiconductor device tester to conduct measurement for characteristic test for a semiconductor device. SOLUTION: When a capacity C formed in a semiconductor device exists in a conductive passage at the measuring for the structure of the semiconductor device, a charge acceleration current 12 to the capacity C is applied additively to a current I1 at the measurement, and at a specified time after that, application of the charge acceleration current 12 is stopped, but only the current I1 at the time of measurement is applied by providing a semiconductor device capacity charge acceleration means 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor,
The present invention relates to a semiconductor device tester which is effective for shortening a measurement time of a breakdown voltage and a breaking current of a semiconductor device such as an ET.

[0002]

2. Description of the Related Art One of the factors that determine the production cost of semiconductor devices such as transistors and FETs is the breakdown voltage (B).
V), the breaking current (leak current: IL), or the length of time required for various measurements for characteristic tests such as current amplification factor (hfe). The measurement of the breakdown voltage (BV) and the cutoff current (leakage current: IL) that cannot be omitted among these various measurements and that requires a long time for the measurement are performed.

In most semiconductor devices, these measurements are required. In the following description, a transistor will be described as an example. Breakdown voltage (collector-emitter withstand voltage: BVCEO) and collector cutoff current (ICBO, I
L) are in a relative relationship, as shown in FIG. These breakdown voltages BV1, BV2 and the cutoff currents IL1, I
In order to efficiently measure L2, a semiconductor device tester has been conventionally used. The semiconductor device tester automatically and sequentially measures the breakdown voltage and the collector cut-off current and one or more other measurements for one or a plurality of semiconductor devices, here, transistors, for example, using a test program as shown below.

Test program example T1 BVCEO MIN = 820 [V] I = 1 [m
A] TIME = 50 [ms] T2 BVCEO MIN = 850 [V] I = 10 [m]
A] TIME = 5 [ms] T3 ICBO MAX = 10 [μA] VCB = 900
[V] TIME = 50 [ms] T4 ICBO MAX = 1 [mA] VCB = 900
[V] TIME = 5 [ms] Tn The above test program example shows a case where the current is different for each of the breakdown voltage measurement and the collector cut-off current measurement. )> 820
[V] Current = 1 [mA] Time = 50 [ms], Test 2 = breakdown voltage (between collector and emitter)> 850
[V] Current = 10 [mA] Time = 5 [ms], Test 3 = Collector cutoff current (between collector and base) <
10 μA Voltage 900 [V] Time = 50 [ms], Test 4 = Collector cut-off current (between collector and base) <
1 [mA] Voltage 900 [V] Time = 5 [ms] This is a test program for measuring test n = ... This test program is sequentially executed from T1 (test 1) to Tn (test n) at the start of measurement, and breakdown voltage measurement and collector cutoff current measurement are performed under different conditions.

FIG. 8 is a circuit diagram showing a conventional breakdown voltage (BVCEO) tester. Here, an actual example of breakdown voltage measurement at a current I = 1 [mA] is shown. In FIG. 8, E is a test DC power supply, R1 is the same resistor, AMP1 is the same amplifier, OUT is an output terminal, and DUT is a transistor under measurement. Here, E = 1 [V] and R1 = 1 [KΩ]. In such a circuit configuration, the current I = 1 [mA]
The voltage EO appearing at the output terminal OUT at the time of measuring the breakdown voltage by flowing the current becomes the breakdown voltage of the transistor under test DUT.

FIG. 9 is a circuit diagram showing a conventional collector cut-off current (IL) tester.
[V] is an actual example of collector cut-off current measurement when the detection range (current) = 10 μA. In FIG. 9, E denotes a test DC power supply, R2 denotes the same resistor, AMP2 denotes the same amplifier, OUT denotes an output terminal, and DUT denotes a transistor to be measured. Here, E = 900 [V] and R2 = 1 MΩ. In such a circuit configuration, voltage = 900 [V]
Output terminal OUT during collector cut-off current measurement with
Of the test resistor R2 = 1M
The value divided by Ω is the collector cutoff current IL of the transistor under test DUT.

[0007]

However, in the above-mentioned conventional tester, the time required for measurement for the characteristic test of a semiconductor device (the measurement time of the breakdown voltage and the collector cut-off current of a transistor) is required. There has been a problem that the production cost has been long.

An object of the present invention is to provide a semiconductor device tester that can reduce the time required for measurement for measuring the characteristics of a semiconductor device (measurement time) and reduce the production cost.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device tester for performing a measurement for a characteristic test of a semiconductor device, wherein a capacitance formed in the semiconductor device is not changed due to the configuration of the semiconductor device. When the current is present in the electric circuit, the current at the time of the measurement is additionally supplied with the current for promoting the charge to the capacity, and after a predetermined time (after the completion of the charging), the current for the charge promoting is stopped. This is attained by providing a semiconductor device capacity charging promoting means for conducting only the current at the time of measurement.

Due to the structure (manufacturing) of a semiconductor device, a capacitance is formed in the semiconductor device. During the measurement for the characteristic test of the semiconductor device, if the capacitance exists in the current path, the measurement voltage or current fluctuates until the capacitance is charged, so that accurate measurement cannot be performed. Therefore, a waiting time until the capacity is fully charged occurs, and the measuring time is lengthened.

[0011] In the present invention, the semiconductor device capacity charging promoting means includes a current for measuring the semiconductor device and a current for promoting the charging of the capacity added to the current, and after a predetermined time, stops supplying the charging promoting current. Only the current at the time of the measurement is supplied, and the measurement is performed.

According to this, the charging to the capacity is performed instantaneously, the measurement time is reduced by the waiting time until the capacity is fully charged, and the production cost can be reduced. In addition,
After a predetermined time (time for charging the capacitor), the supply of the current for accelerating the charging is stopped, so that there is no adverse effect (measurement error) due to the provision of the device for accelerating the capacitor charging.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, prior to the description of a specific embodiment of the present invention, its measurement principle will be described. First, the principle of measuring the breakdown voltage (BVCEO) according to the present invention will be described with reference to FIG. In FIG. 5, E is a test DC power supply, R1 is the same resistor, AMP1 is the same amplifier, OUT
Is an output terminal, and DUT is a transistor to be measured. C is the capacitance between the collector and the emitter of the transistor under test DUT.
Usually, it is formed without intention.

In such a circuit, the voltage EO that appears at the output terminal OUT when the breakdown voltage is measured by passing the current I becomes the breakdown voltage of the transistor under test DUT. However, in practice, a capacitance C exists between the collector and the emitter of the transistor under test DUT as shown by a broken line.
And the resistance value of the above, an integrating circuit is formed. Therefore, until the breakdown voltage is reached, the output voltage EO is calculated by the following equation (1).
Is determined. EO = (I · t) / C (1) where t is a measurement time (time until a breakdown voltage is reached),
I is the current (current value) flowing through the current path during measurement.

As can be seen from the equation (1), the time t required to reach the breakdown voltage (measurement time) is determined by the magnitude of the current I (supply current value I). It can be seen that the measurement is performed quickly, that is, the measurement time is reduced.

Next, the collector cutoff current (I
The measurement principle of L) will be described with reference to FIG. In FIG. 6, E is a test DC power supply, R2 is the same resistance, AMP
2 is the same amplifier, OUT is an output terminal, and DUT is a transistor to be measured. C is the capacitance between the collector and the emitter of the transistor under test DUT.
In general, it is formed unintentionally due to the structure (production).

In such a circuit, when a voltage E [V] is applied, an output voltage EO [V] is obtained. At this time, EO = IL · R2 (IL is the value of the interrupting current, R2 is the value of the test resistor R2, and so on).
The breaking current (value) IL is a value obtained by the following equation (2). IL = EO / R2 (2) Actually, however, the capacitance C exists between the collector and the emitter of the transistor under test DUT as shown by the broken line. Not a current (value). The charging time of the capacitor C is equal to the resistance R2
, The measurement time becomes shorter as the resistance R2 becomes smaller. The value of R2 is determined by the current detection range.

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device tester according to the present invention. Here, an example of a semiconductor device tester in which the present invention is applied to measurement of a breakdown voltage (BVCEO) is shown. In FIG. 1, E is a test DC power supply, R1a is the same resistance, and AMP is
1 is the same amplifier, OUT is an output terminal, and DUT is a transistor to be measured. Here, the transistor under test DUT is connected in parallel with the test amplifier AMP1, and the test resistor R1a is connected to the test DC power supply E and the test amplifier AMP1.
1 are connected to each other. The test resistor R1a
Corresponds to the test resistor R1.

Reference numeral 11 denotes a transistor capacity charge promotion circuit as a semiconductor device capacity charge promotion means, which applies a current I (I1) at the time of breakdown voltage measurement to the capacity C (capacitance between the collector and the emitter of the transistor DUT to be measured). The charging promotion current I2 is additionally supplied, and after a predetermined time, the supply of the charging promotion current I2 is stopped, and the current I (I
The energization of only 1) is performed. The transistor capacitance charge promotion circuit 11 here comprises a resistor R1b, a switch SW1, and a control circuit CTRL.

The resistor R1b and the switch SW1 are connected in series, and are connected in parallel to the test resistor R1a. The switch SW1 is turned on when the breakdown voltage is measured by the control circuit CTRL, and is turned off after a lapse of time when the capacitor C is fully charged. Here, E = 1 [V], R
1a = 1 [KΩ] and R1b = 100 [Ω]. When the switch SW1 is turned on, 1 [m] is applied to the test resistor R1a side.
A] (test current) I1 and 10 times the current (mA) (charge accelerating current) I2 on the resistor R1b side.
Flows, and a current of 10 + 1 = 11 [mA] flows through the capacitance C of the transistor DUT to be charged. When the switch SW1 is turned off, that is, when the breakdown voltage is measured, only the current (test current) I1 of 1 mA flows, and the breakdown voltage is measured (see FIG. 2).

In such a circuit configuration, the current I = 1
The voltage EO that appears at the output terminal OUT when the breakdown voltage is measured by flowing [mA] becomes the breakdown voltage of the transistor under test DUT.

According to the tester of the present invention, for example, the current I
In the breakdown voltage measurement with (I1) = 1 [mA], a current (charge promotion current) I2 of 10 [mA] is added until the breakdown voltage is reached.
The charging of the capacitance C between the collector and the emitter of the UT is promoted. When the breakdown voltage is reached, the current is returned to the measurement current I (I1) of 1 [mA], and the intended measurement (breakdown voltage measurement) is performed. As a result, the breakdown voltage measurement time can be speeded up almost ten times as compared with the conventional tester (measurement circuit).

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor device tester according to the present invention. FIG. 3 shows an example of a semiconductor device tester in which the present invention is applied to the measurement of the collector cutoff current (IL).
In E, DC is a test DC power supply, R2a is the same resistance, A
MP2 is the same amplifier, OUT is an output terminal, and DUT is a transistor to be measured. Here, the measured transistor DU
T is connected between the test DC power supply E and the test amplifier AMP2, and the test resistor R2a is connected in parallel to the test amplifier AMP2. The test resistor R
2a corresponds to the test resistor R2.

Reference numeral 31 denotes a transistor capacity charge promotion circuit as a semiconductor device capacity charge promotion means. The current I (I3) at the time of measuring the collector cutoff current is applied to the capacity (capacity between the collector and the emitter of the transistor DUT to be measured) C. Is supplied with the current I4 for accelerating the charging, and after a predetermined time, the current I4 for accelerating the charging is stopped, and only the current I (I3) at the time of measuring the collector cutoff current is supplied. The transistor capacitance charge promotion circuit 31 here comprises a resistor R2b, a switch SW2, and a control circuit CTRL.

The resistor R2b and the switch SW2 are connected in series, and are connected in parallel to the test resistor R2a. The switch SW2 is turned on when the control circuit CTRL measures the collector cutoff current, and is turned off after a lapse of time when the capacitor C is fully charged. Here, E = 90
0 [V], R2a = 1 [MΩ], R2b = 1 [KΩ], and when the switch SW2 is turned on, the charge promoting current I4 flows to the resistor R2b side, and the capacitance C of the transistor under test DUT is charged. Promoted. When the switch SW2 is turned off, that is, when the collector cutoff current IL is measured, only the test current I3 flows, and the collector cutoff current is measured (see FIG. 4).

In such a circuit configuration, voltage = 90
The value obtained by dividing the voltage EO appearing at the output terminal OUT at the time of measuring the collector cutoff current by applying 0 [V] by the resistance value of the test resistor R2a = 1 MΩ is the collector cutoff current IL of the transistor under test DUT.

According to the tester of the present invention described above, the switch SW2 is turned on until the capacitance C between the collector and the emitter of the transistor under test DUT is fully charged, thereby promoting the charging of the capacitance C. When the capacitor C is fully charged, the switch SW2 is turned off, and the intended breaking current measurement, here, the breaking current measurement in the range of 10 μA (test resistance R2a = 1 MΩ) is performed. As a result, the cut-off current measurement time is significantly increased compared to the conventional tester (measurement circuit).

In any of the measurement of the breakdown voltage and the collector cut-off current, the additional resistance (which does not cause a destruction between the collector and the emitter of the transistor under test DUT and does not cause any adverse effect to lower the accuracy of the measurement result). R
It goes without saying that the resistance values of 1b, R2b) are selected.

In the above-described embodiment, the description has been made by taking the measurement for each transistor as an example. However, a configuration may be adopted in which a plurality of transistors are measured simultaneously or sequentially switched. In addition, an I / O having a plurality of transistors
The present invention may be applied to measurement of C (integrated circuit).

In the above embodiment, the case where the semiconductor device to be measured is an NPN transistor has been described as an example. However, a PNP transistor or another semiconductor device, such as an FET or a rectifier, is used. You may.

[0031]

As described above, according to the present invention, it is possible to reduce the time (measurement time) required for performing the measurement for the characteristic test of the semiconductor device and reduce the production cost. effective.

[0032]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device tester of the present invention.

FIG. 2 is a time chart for explaining the operation of the semiconductor device tester of the present invention shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor device tester of the present invention.

FIG. 4 is a time chart for explaining the operation of the semiconductor device tester of the present invention shown in FIG. 3;

FIG. 5 is a circuit diagram illustrating a principle of measuring a breakdown voltage according to the present invention.

FIG. 6 is a circuit diagram for explaining a principle of measuring a collector cutoff current according to the present invention.

FIG. 7 is a characteristic diagram showing a relative relationship between a breakdown voltage of a transistor and a collector cutoff current.

FIG. 8 is a circuit diagram showing a breakdown voltage tester of a conventional transistor.

FIG. 9 is a circuit diagram showing a conventional collector cut-off current tester of a transistor.

[Explanation of symbols]

E Test DC power supply R1, R1a, R2, R2a Test resistor AMP1, AMP2 Test amplifier OUT Output terminal DUT Transistor under test 11, 31 Transistor capacitance charge promotion circuit (semiconductor device capacitance charge promotion means) C Collector of transistor under test -Emitter capacitance R1b, R2b Resistance SW1, SW2 Switch CTRL Control circuit

Claims (3)

[Claims] 1. A semiconductor device tester for performing a measurement for a characteristic test of a semiconductor device, wherein a capacitance formed in the semiconductor device is present in a current path during the measurement due to a configuration of the semiconductor device. Then, a current for promoting the charging of the capacity is additionally supplied to the current at the time of the measurement, and after a predetermined time (after completion of charging), the current for the promotion of the charge is stopped, and only the current at the time of the measurement is supplied. A semiconductor device tester, comprising: a semiconductor device capacity charging promoting means for performing the following. 2. The semiconductor device tester according to claim 1, wherein the measurement for the characteristic test is a breakdown voltage measurement. 3. The semiconductor device tester according to claim 1, wherein the measurement for the characteristic test is a breaking current measurement.