JPS51112269A - Wire bonding method - Google Patents

Wire bonding method

Info

Publication number
JPS51112269A
JPS51112269A JP50036715A JP3671575A JPS51112269A JP S51112269 A JPS51112269 A JP S51112269A JP 50036715 A JP50036715 A JP 50036715A JP 3671575 A JP3671575 A JP 3671575A JP S51112269 A JPS51112269 A JP S51112269A
Authority
JP
Japan
Prior art keywords
wire bonding
bonding method
bonding
shortcircuiting
deforming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50036715A
Other languages
Japanese (ja)
Inventor
Mitsunori Karasawa
Hideki Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50036715A priority Critical patent/JPS51112269A/en
Publication of JPS51112269A publication Critical patent/JPS51112269A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To surely prevent a tab from shortcircuiting by deforming an inner lead upon bonding it and making wire bonding in that condition.
COPYRIGHT: (C)1976,JPO&Japio
JP50036715A 1975-03-28 1975-03-28 Wire bonding method Pending JPS51112269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50036715A JPS51112269A (en) 1975-03-28 1975-03-28 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50036715A JPS51112269A (en) 1975-03-28 1975-03-28 Wire bonding method

Publications (1)

Publication Number Publication Date
JPS51112269A true JPS51112269A (en) 1976-10-04

Family

ID=12477438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50036715A Pending JPS51112269A (en) 1975-03-28 1975-03-28 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS51112269A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130972U (en) * 1977-03-25 1978-10-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130972U (en) * 1977-03-25 1978-10-17

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