JPS51150973A - Manufacture process for a semiconductor device - Google Patents

Manufacture process for a semiconductor device

Info

Publication number
JPS51150973A
JPS51150973A JP50074902A JP7490275A JPS51150973A JP S51150973 A JPS51150973 A JP S51150973A JP 50074902 A JP50074902 A JP 50074902A JP 7490275 A JP7490275 A JP 7490275A JP S51150973 A JPS51150973 A JP S51150973A
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacture process
conected
beforehand
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50074902A
Other languages
English (en)
Inventor
Koichi Konakawa
Yoshio Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP50074902A priority Critical patent/JPS51150973A/ja
Publication of JPS51150973A publication Critical patent/JPS51150973A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
JP50074902A 1975-06-19 1975-06-19 Manufacture process for a semiconductor device Pending JPS51150973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50074902A JPS51150973A (en) 1975-06-19 1975-06-19 Manufacture process for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50074902A JPS51150973A (en) 1975-06-19 1975-06-19 Manufacture process for a semiconductor device

Publications (1)

Publication Number Publication Date
JPS51150973A true JPS51150973A (en) 1976-12-24

Family

ID=13560773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50074902A Pending JPS51150973A (en) 1975-06-19 1975-06-19 Manufacture process for a semiconductor device

Country Status (1)

Country Link
JP (1) JPS51150973A (ja)

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