JPS5224084A - Semiconductor manufacturing rpocess - Google Patents

Semiconductor manufacturing rpocess

Info

Publication number
JPS5224084A
JPS5224084A JP50100813A JP10081375A JPS5224084A JP S5224084 A JPS5224084 A JP S5224084A JP 50100813 A JP50100813 A JP 50100813A JP 10081375 A JP10081375 A JP 10081375A JP S5224084 A JPS5224084 A JP S5224084A
Authority
JP
Japan
Prior art keywords
wiring
rpocess
semiconductor manufacturing
film
moat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50100813A
Other languages
Japanese (ja)
Inventor
Masanori Fukumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50100813A priority Critical patent/JPS5224084A/en
Publication of JPS5224084A publication Critical patent/JPS5224084A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE: The lst insulating film 12 such as silicon dioxide formed on semiconductor substrate 11 is coated with resis 13 to form negative patterns of wiring. With resist 13 used in masking material, the 1st insulating film 12 is selectively etched by a spectified depth to form wiring moat 14. Then, wiring metalic film 15 having a depth equal to that of moat 14 is formed on the entire surface, and resist 13 and metalic film 15 is selectively eliminated to provide a flat wiring surface. The process is repeated to form a multi-layer wiring.
COPYRIGHT: (C)1977,JPO&Japio
JP50100813A 1975-08-19 1975-08-19 Semiconductor manufacturing rpocess Pending JPS5224084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50100813A JPS5224084A (en) 1975-08-19 1975-08-19 Semiconductor manufacturing rpocess

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50100813A JPS5224084A (en) 1975-08-19 1975-08-19 Semiconductor manufacturing rpocess

Publications (1)

Publication Number Publication Date
JPS5224084A true JPS5224084A (en) 1977-02-23

Family

ID=14283783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50100813A Pending JPS5224084A (en) 1975-08-19 1975-08-19 Semiconductor manufacturing rpocess

Country Status (1)

Country Link
JP (1) JPS5224084A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532969U (en) * 1976-06-26 1978-01-12
JPS55146933A (en) * 1979-05-04 1980-11-15 Nec Corp Manufacturing of integrated element
JPS58122752A (en) * 1982-01-18 1983-07-21 Toshiba Corp Preparation of semiconductor device
JPS60115246A (en) * 1983-11-03 1985-06-21 エスジーエス―トムソン　マイクロエレクトロニクス　インコーポレイテッド Method of forming layer of conductor patterned on integratedcircuit
US5420068A (en) * 1991-09-27 1995-05-30 Nec Corporation Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532969U (en) * 1976-06-26 1978-01-12
JPS55146933A (en) * 1979-05-04 1980-11-15 Nec Corp Manufacturing of integrated element
JPS58122752A (en) * 1982-01-18 1983-07-21 Toshiba Corp Preparation of semiconductor device
JPS60115246A (en) * 1983-11-03 1985-06-21 エスジーエス―トムソン　マイクロエレクトロニクス　インコーポレイテッド Method of forming layer of conductor patterned on integratedcircuit
US5420068A (en) * 1991-09-27 1995-05-30 Nec Corporation Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure

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