JPS5268366A - Solder vamp formation onto semiconductor substrate - Google Patents

Solder vamp formation onto semiconductor substrate

Info

Publication number
JPS5268366A
JPS5268366A JP50143965A JP14396575A JPS5268366A JP S5268366 A JPS5268366 A JP S5268366A JP 50143965 A JP50143965 A JP 50143965A JP 14396575 A JP14396575 A JP 14396575A JP S5268366 A JPS5268366 A JP S5268366A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
solder
onto semiconductor
formation onto
vamp formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50143965A
Other languages
English (en)
Other versions
JPS5935178B2 (ja
Inventor
Kazuo Umeyama
Zenzo Tajima
Kunio Hatano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50143965A priority Critical patent/JPS5935178B2/ja
Publication of JPS5268366A publication Critical patent/JPS5268366A/ja
Publication of JPS5935178B2 publication Critical patent/JPS5935178B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Electrodes Of Semiconductors (AREA)
JP50143965A 1975-12-05 1975-12-05 半導体基板上の電極部に半田バンプを形成する方法 Expired JPS5935178B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50143965A JPS5935178B2 (ja) 1975-12-05 1975-12-05 半導体基板上の電極部に半田バンプを形成する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50143965A JPS5935178B2 (ja) 1975-12-05 1975-12-05 半導体基板上の電極部に半田バンプを形成する方法

Publications (2)

Publication Number Publication Date
JPS5268366A true JPS5268366A (en) 1977-06-07
JPS5935178B2 JPS5935178B2 (ja) 1984-08-27

Family

ID=15351161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50143965A Expired JPS5935178B2 (ja) 1975-12-05 1975-12-05 半導体基板上の電極部に半田バンプを形成する方法

Country Status (1)

Country Link
JP (1) JPS5935178B2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003163232A (ja) * 2002-11-21 2003-06-06 Fujitsu Ltd 予備ハンダの形成方法
US7378296B2 (en) 2003-02-25 2008-05-27 Kyocera Corporation Print mask and method of manufacturing electronic components using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003163232A (ja) * 2002-11-21 2003-06-06 Fujitsu Ltd 予備ハンダの形成方法
US7378296B2 (en) 2003-02-25 2008-05-27 Kyocera Corporation Print mask and method of manufacturing electronic components using the same
US7638420B2 (en) 2003-02-25 2009-12-29 Kyocera Corporation Print mask and method of manufacturing electronic components using the same

Also Published As

Publication number Publication date
JPS5935178B2 (ja) 1984-08-27

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