JPS5485672A - Semiconcutor device - Google Patents

Semiconcutor device

Info

Publication number
JPS5485672A
JPS5485672A JP15393977A JP15393977A JPS5485672A JP S5485672 A JPS5485672 A JP S5485672A JP 15393977 A JP15393977 A JP 15393977A JP 15393977 A JP15393977 A JP 15393977A JP S5485672 A JPS5485672 A JP S5485672A
Authority
JP
Japan
Prior art keywords
copper foil
rolled copper
reliability
lead frame
semiconcutor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15393977A
Other languages
Japanese (ja)
Other versions
JPS6126220B2 (en
Inventor
Hiroshi Yokota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15393977A priority Critical patent/JPS5485672A/en
Publication of JPS5485672A publication Critical patent/JPS5485672A/en
Publication of JPS6126220B2 publication Critical patent/JPS6126220B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To increase the manufacturing yield rate and the reliability, by using rolled copper foil.
CONSTITUTION: The lead frame is formed by using the rolled copper foil with 70 or more Vickers hardness. Since the rolled copper foil is less in surface unevenness resulting in ease of control for platng amount, and since the plated surface is also flat, the short circuit between the lead frame and the semiconductor as conventional can be remarkably reduced. Further, the bending strength is strong, no crack or damage is caused, and the reliability is great.
COPYRIGHT: (C)1979,JPO&Japio
JP15393977A 1977-12-20 1977-12-20 Semiconcutor device Granted JPS5485672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15393977A JPS5485672A (en) 1977-12-20 1977-12-20 Semiconcutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15393977A JPS5485672A (en) 1977-12-20 1977-12-20 Semiconcutor device

Publications (2)

Publication Number Publication Date
JPS5485672A true JPS5485672A (en) 1979-07-07
JPS6126220B2 JPS6126220B2 (en) 1986-06-19

Family

ID=15573374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15393977A Granted JPS5485672A (en) 1977-12-20 1977-12-20 Semiconcutor device

Country Status (1)

Country Link
JP (1) JPS5485672A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387725U (en) * 1986-11-27 1988-06-08

Also Published As

Publication number Publication date
JPS6126220B2 (en) 1986-06-19

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