JPS5544701A - Manufacturing transistor - Google Patents

Manufacturing transistor

Info

Publication number
JPS5544701A
JPS5544701A JP11655478A JP11655478A JPS5544701A JP S5544701 A JPS5544701 A JP S5544701A JP 11655478 A JP11655478 A JP 11655478A JP 11655478 A JP11655478 A JP 11655478A JP S5544701 A JPS5544701 A JP S5544701A
Authority
JP
Japan
Prior art keywords
film
layer
emitter
sio
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11655478A
Other languages
Japanese (ja)
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11655478A priority Critical patent/JPS5544701A/en
Publication of JPS5544701A publication Critical patent/JPS5544701A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To simply manufacture super-miniaturized transistors by diffusing emitter-forming impurities into semiconductor deposits from base diffused materials, performing emitter diffusion with the deposits as impurity sources, and accomplishing these operations in one process.
CONSTITUTION: An SiO2 film 12 and a PSG film 14 are formed on the surface of an N-type silicon substrate 10 by a specified method, then a base-difusion opening 16 is formed. Furthermore, a base layer 18 is formed by selectively diffusing B on the surface of the substrate 10, then, silicon-deposit layers 20A and 20B are formed by depositing silicon on the layer 18 and the film 14. After an SiO2 film 22 is formed on the surface of the layers 20A and 20B, emitter impurities of the film 14 is diffused into the layer 20B by heat treatment. Then, oxidization and difusion treatments are conducted in the atmosphere at a specified temperature with the layer 20B as an impurity source, thereby an N+ emitter layer 24 is formed and an SiO2 film 26 is formed on the layer 20. Thereafter, the thin portion 26A of the film 26 is removed with the film 26B being remained, and an epitaxially grown layer 28 is formed on the surface of the layer 18.
COPYRIGHT: (C)1980,JPO&Japio
JP11655478A 1978-09-25 1978-09-25 Manufacturing transistor Pending JPS5544701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11655478A JPS5544701A (en) 1978-09-25 1978-09-25 Manufacturing transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11655478A JPS5544701A (en) 1978-09-25 1978-09-25 Manufacturing transistor

Publications (1)

Publication Number Publication Date
JPS5544701A true JPS5544701A (en) 1980-03-29

Family

ID=14689982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11655478A Pending JPS5544701A (en) 1978-09-25 1978-09-25 Manufacturing transistor

Country Status (1)

Country Link
JP (1) JPS5544701A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331166A (en) * 1986-07-24 1988-02-09 Nec Corp Semiconductor device
JPS63147845U (en) * 1987-03-19 1988-09-29
JPS63503185A (en) * 1986-04-23 1988-11-17 エイ・ティ・アンド・ティ・コーポレーション Semiconductor device manufacturing process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63503185A (en) * 1986-04-23 1988-11-17 エイ・ティ・アンド・ティ・コーポレーション Semiconductor device manufacturing process
JPS6331166A (en) * 1986-07-24 1988-02-09 Nec Corp Semiconductor device
JPS63147845U (en) * 1987-03-19 1988-09-29

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