JPS5565457A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5565457A
JPS5565457A JP14029578A JP14029578A JPS5565457A JP S5565457 A JPS5565457 A JP S5565457A JP 14029578 A JP14029578 A JP 14029578A JP 14029578 A JP14029578 A JP 14029578A JP S5565457 A JPS5565457 A JP S5565457A
Authority
JP
Japan
Prior art keywords
layer
diode
fet2
drain
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14029578A
Other languages
Japanese (ja)
Other versions
JPS6043029B2 (en
Inventor
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP53140295A priority Critical patent/JPS6043029B2/en
Publication of JPS5565457A publication Critical patent/JPS5565457A/en
Publication of JPS6043029B2 publication Critical patent/JPS6043029B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: To reduce the power consumption of static type memory device and achieve high integration by means of a very simple structure.
CONSTITUTION: An n+-layers 11 and 12 on the surface of p--type semiconductor substrate 10 are made into a drain and a source. Electrode 14 on surface insulating film 13 between these is made into a gate, and thereby switching element 2 is formed. p- Epitaxial layer 15 and p+-layer 16 are laminated on n-layer 12, and thereby diode 1 is formed. The control output is produced by connecting p+-layer 16 and drain 11. n+-Layer 12, together with substrate 10, is grounded by grounded electrode 17. In this structure, when FET2 as a switching element is turned off, the barrier voltage of the pn junction is outputted to the anode terminal of diode 1; when FET2 is turned on, the potential difference between both terminals of diode 1 becomes zero, and the output is zero. Consequently, it is possible to store binary information. Further, there is no need for information maintaining current, so that the power consumption is reduced and the occupied area can be made smaller than the conventional device.
COPYRIGHT: (C)1980,JPO&Japio
JP53140295A 1978-11-13 1978-11-13 semiconductor memory device Expired JPS6043029B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53140295A JPS6043029B2 (en) 1978-11-13 1978-11-13 semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53140295A JPS6043029B2 (en) 1978-11-13 1978-11-13 semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS5565457A true JPS5565457A (en) 1980-05-16
JPS6043029B2 JPS6043029B2 (en) 1985-09-26

Family

ID=15265455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53140295A Expired JPS6043029B2 (en) 1978-11-13 1978-11-13 semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6043029B2 (en)

Also Published As

Publication number Publication date
JPS6043029B2 (en) 1985-09-26

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