JPS558066A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS558066A
JPS558066A JP8089378A JP8089378A JPS558066A JP S558066 A JPS558066 A JP S558066A JP 8089378 A JP8089378 A JP 8089378A JP 8089378 A JP8089378 A JP 8089378A JP S558066 A JPS558066 A JP S558066A
Authority
JP
Japan
Prior art keywords
layer
spot
mono
crystalline
ranges
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8089378A
Other languages
Japanese (ja)
Inventor
Takeo Yoshimi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8089378A priority Critical patent/JPS558066A/en
Publication of JPS558066A publication Critical patent/JPS558066A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE: To provide a plurality of spot-like mono-crystalline Si layers over the porous Si layer provided on an Si substrate and surround said spot-like layers with said porous layer oxidized, for decreasing the interface stress of spot-like ranges and obtaining an isolation construction.
CONSTITUTION: Porous Si layer 12 is deposited on an mono-crystalline Si substrate 10, and gas phase breeding of mono-crystalline Si layer 14 is made thereon. Next, masks 16AW16C of Si3N4 for example are provided on said layer 14 to correspond to a required spot like range formation pattern, and spot-like mono-crystalline ranges 14AW16C are formed by the selective etching of said layer 14. Thereafter, said porous layer 12 is changed into SiO2 layer 13 by oxidaition. At this time, said ranges 14AW14C are not oxidized since the oxidaition speed of said porous layer 12 is very high. Next, a circuit element is prepared in said ranges 14AW14C thus surrounded with SiO2 layers 13a and 13b, the whole surface of said substrate 10 is covered with passivation film 18, opening are provided, and electrode wiring 20 is fitted.
COPYRIGHT: (C)1980,JPO&Japio
JP8089378A 1978-07-05 1978-07-05 Manufacture of semiconductor Pending JPS558066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8089378A JPS558066A (en) 1978-07-05 1978-07-05 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8089378A JPS558066A (en) 1978-07-05 1978-07-05 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPS558066A true JPS558066A (en) 1980-01-21

Family

ID=13731032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8089378A Pending JPS558066A (en) 1978-07-05 1978-07-05 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS558066A (en)

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