JPS5586125A - Mounting method of semiconductor device - Google Patents

Mounting method of semiconductor device

Info

Publication number
JPS5586125A
JPS5586125A JP16057378A JP16057378A JPS5586125A JP S5586125 A JPS5586125 A JP S5586125A JP 16057378 A JP16057378 A JP 16057378A JP 16057378 A JP16057378 A JP 16057378A JP S5586125 A JPS5586125 A JP S5586125A
Authority
JP
Japan
Prior art keywords
backing sheet
substrate
bonding agent
processes
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16057378A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Tominaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP16057378A priority Critical patent/JPS5586125A/en
Publication of JPS5586125A publication Critical patent/JPS5586125A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To decrease the number of the processes of manufacture by a method wherein the mounting of a semiconductor element and the joining together of a backing sheet and a circuit substrate can continuously be executed. CONSTITUTION:A backing sheet 13 such as a laminated one is placed on a heater board 16 and a bonding agent 14 is heated beforehand, then a semiconductor element 15 is heat-pressed via protective material 17a, using an air chuck. Next the backing sheet 13 is transferred onto a heater board 18 which is under a circuit substrate 10 and heated. The element 15 is mounted in a hole 11 made in the substrate 10, before being pressed by a tool 19. The substrate 10 and the backing sheet 13 are fixed together firmly by the use of the bonding agent 14 and burned. Next a lead 12 on the substrate 10 and the external electrode of the element 15 are connected by a gold wire 20, and the circuit is sealed by resin. In this manner the number of processes can be decreased through continuous operations, using the bonding agent coated on the main surface of the backing sheet.
JP16057378A 1978-12-22 1978-12-22 Mounting method of semiconductor device Pending JPS5586125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16057378A JPS5586125A (en) 1978-12-22 1978-12-22 Mounting method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16057378A JPS5586125A (en) 1978-12-22 1978-12-22 Mounting method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5586125A true JPS5586125A (en) 1980-06-28

Family

ID=15717879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16057378A Pending JPS5586125A (en) 1978-12-22 1978-12-22 Mounting method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5586125A (en)

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