JPS647643A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS647643A
JPS647643A JP62161252A JP16125287A JPS647643A JP S647643 A JPS647643 A JP S647643A JP 62161252 A JP62161252 A JP 62161252A JP 16125287 A JP16125287 A JP 16125287A JP S647643 A JPS647643 A JP S647643A
Authority
JP
Japan
Prior art keywords
base
resin
cap
refuse
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62161252A
Other languages
Japanese (ja)
Inventor
Yoshimichi Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62161252A priority Critical patent/JPS647643A/en
Publication of JPS647643A publication Critical patent/JPS647643A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the lowering of the reliability of a semiconductor device due to refuse and dust intruding into a package by coating the internal surfaces of a base and a cap for the package with a resin attracting refuse, dust, etc. CONSTITUTION:In a semiconductor device hermetically sealing a semiconductor element chip 3 loaded onto a base 1 for a package by a cap 6, etc., the internal surfaces of the base 1 and the cap 6 are coated with a resin 8 attracting X such as refuse, dust. The semiconductor element chip 3 is bonded with a cavity 2 formed to the top face of the base 1 such as a ceramic base 1, and the semiconductor element chip 3 and a lead frame 4 are electrically connected by bonding wires 5. The base 1 is covered with a ceramics cap 6, and the base 1 and the cap 6 are hermetically sealed with low-melting-point glass 7. The rear of the ceramic cap 6 is coated with the resin 8 at that time, and a resin generating static electricity on the surface after thermosetting is used as the resin 8. A polyimide resin, a silicone resin, etc., are employed.
JP62161252A 1987-06-30 1987-06-30 Semiconductor device Pending JPS647643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161252A JPS647643A (en) 1987-06-30 1987-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161252A JPS647643A (en) 1987-06-30 1987-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS647643A true JPS647643A (en) 1989-01-11

Family

ID=15731553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161252A Pending JPS647643A (en) 1987-06-30 1987-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS647643A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0310544U (en) * 1989-06-15 1991-01-31
JP2007266195A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed wiring board and manufacturing method thereof
JP2009038363A (en) * 2007-07-09 2009-02-19 Panasonic Corp Rigid flexible printed wiring board and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0310544U (en) * 1989-06-15 1991-01-31
JP2007266195A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed wiring board and manufacturing method thereof
JP2009038363A (en) * 2007-07-09 2009-02-19 Panasonic Corp Rigid flexible printed wiring board and manufacturing method thereof

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