JPS5629362A - Semiconductor dynamic memory - Google Patents
Semiconductor dynamic memoryInfo
- Publication number
- JPS5629362A JPS5629362A JP10621579A JP10621579A JPS5629362A JP S5629362 A JPS5629362 A JP S5629362A JP 10621579 A JP10621579 A JP 10621579A JP 10621579 A JP10621579 A JP 10621579A JP S5629362 A JPS5629362 A JP S5629362A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- substrate
- layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To obtain a high integrity memory device by a VMOS technique by forming an N type memory region on a P<-> type epitaxial layer on a P<+> type Si substrate by self-diffusion with its density of P<+>>N>P<->. CONSTITUTION:B is selectively added to a P<+> type Si substrate added with P and a plane <100>, and a P<-> type epitaxial layer 3 is laminated thereon. At this time a thin N type memory region 2 is formed owing to the difference of rediffusion of the P and the B. Then, an N<+> type bit region 4 is formed on the upper portion of the region 2, an SiO2 film 5 is coated thereon, an opening is perforated at the film 5, is anisotripically etched to form a V-shaped groove 6 to divide the regions 4 and 2 into two. Since the layer 2 is thin and has no punch-through therebetween, the V- shaped groove may be reduced to improve the integrity. Subsequently, an SiO2 film 7 is coated on the oblique surfaces of the groove, and a polysilicon word line 8 is formed thereon. The junction capacity between the N type layer 2 and the P<+> type substrate stores charge, so that the oblique surfaces of the groove under the work line 8 becomes the N type channel of the VMOST. This configuration can obtain a high integrity and preferable area efficiency in memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10621579A JPS5629362A (en) | 1979-08-20 | 1979-08-20 | Semiconductor dynamic memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10621579A JPS5629362A (en) | 1979-08-20 | 1979-08-20 | Semiconductor dynamic memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5629362A true JPS5629362A (en) | 1981-03-24 |
Family
ID=14427922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10621579A Pending JPS5629362A (en) | 1979-08-20 | 1979-08-20 | Semiconductor dynamic memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5629362A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5016067A (en) * | 1988-04-11 | 1991-05-14 | Texas Instruments Incorporated | Vertical MOS transistor |
| US5016068A (en) * | 1988-04-15 | 1991-05-14 | Texas Instruments Incorporated | Vertical floating-gate transistor |
| US5071782A (en) * | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
| US5124764A (en) * | 1986-10-21 | 1992-06-23 | Texas Instruments Incorporated | Symmetric vertical MOS transistor with improved high voltage operation |
| US5160491A (en) * | 1986-10-21 | 1992-11-03 | Texas Instruments Incorporated | Method of making a vertical MOS transistor |
-
1979
- 1979-08-20 JP JP10621579A patent/JPS5629362A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124764A (en) * | 1986-10-21 | 1992-06-23 | Texas Instruments Incorporated | Symmetric vertical MOS transistor with improved high voltage operation |
| US5160491A (en) * | 1986-10-21 | 1992-11-03 | Texas Instruments Incorporated | Method of making a vertical MOS transistor |
| US5016067A (en) * | 1988-04-11 | 1991-05-14 | Texas Instruments Incorporated | Vertical MOS transistor |
| US5016068A (en) * | 1988-04-15 | 1991-05-14 | Texas Instruments Incorporated | Vertical floating-gate transistor |
| US5071782A (en) * | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
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