JPS5650532A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5650532A
JPS5650532A JP12541179A JP12541179A JPS5650532A JP S5650532 A JPS5650532 A JP S5650532A JP 12541179 A JP12541179 A JP 12541179A JP 12541179 A JP12541179 A JP 12541179A JP S5650532 A JPS5650532 A JP S5650532A
Authority
JP
Japan
Prior art keywords
film
poly
substrate
mos
oxidized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12541179A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6235268B2 (2
Inventor
Yasunobu Osa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12541179A priority Critical patent/JPS5650532A/ja
Priority to US06/174,434 priority patent/US4356041A/en
Priority to DE19803036960 priority patent/DE3036960A1/de
Publication of JPS5650532A publication Critical patent/JPS5650532A/ja
Publication of JPS6235268B2 publication Critical patent/JPS6235268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6316—Formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP12541179A 1979-10-01 1979-10-01 Manufacture of semiconductor device Granted JPS5650532A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP12541179A JPS5650532A (en) 1979-10-01 1979-10-01 Manufacture of semiconductor device
US06/174,434 US4356041A (en) 1979-10-01 1980-08-01 Method of fabricating a mis-type device by using a gate electrode and selectively implanted nitride layer
DE19803036960 DE3036960A1 (de) 1979-10-01 1980-09-30 Verfahren zur herstellung einer halbleitervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12541179A JPS5650532A (en) 1979-10-01 1979-10-01 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5650532A true JPS5650532A (en) 1981-05-07
JPS6235268B2 JPS6235268B2 (2) 1987-07-31

Family

ID=14909437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12541179A Granted JPS5650532A (en) 1979-10-01 1979-10-01 Manufacture of semiconductor device

Country Status (3)

Country Link
US (1) US4356041A (2)
JP (1) JPS5650532A (2)
DE (1) DE3036960A1 (2)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409722A (en) * 1980-08-29 1983-10-18 International Business Machines Corporation Borderless diffusion contact process and structure
US4476622A (en) * 1981-12-24 1984-10-16 Gte Laboratories Inc. Recessed gate static induction transistor fabrication
DE3329074A1 (de) * 1983-08-11 1985-02-28 Siemens AG, 1000 Berlin und 8000 München Verhinderung der oxidationsmitteldiffusion bei der herstellung von halbleiterschichtanordnungen
US5200802A (en) * 1991-05-24 1993-04-06 National Semiconductor Corporation Semiconductor ROM cell programmed using source mask
JPH0634657A (ja) * 1992-04-01 1994-02-10 Sony Tektronix Corp 電気供給装置
US5432103A (en) * 1992-06-22 1995-07-11 National Semiconductor Corporation Method of making semiconductor ROM cell programmed using source mask
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US6156603A (en) * 1998-12-01 2000-12-05 United Mircroelectronics Corp. Manufacturing method for reducing the thickness of a dielectric layer
US6153538A (en) * 1999-05-03 2000-11-28 Advanced Micro Devices, Inc. Method of making MOSFET with ultra-thin gate oxide
WO2007135620A1 (en) * 2006-05-18 2007-11-29 Nxp B.V. Method of increasing the quality factor of an inductor in a semiconductor device
US7960243B2 (en) * 2007-05-31 2011-06-14 Freescale Semiconductor, Inc. Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51148362A (en) * 1975-06-04 1976-12-20 Philips Nv Semiconductor device and method of making the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4060827A (en) * 1967-02-03 1977-11-29 Hitachi, Ltd. Semiconductor device and a method of making the same
US3798752A (en) * 1971-03-11 1974-03-26 Nippon Electric Co Method of producing a silicon gate insulated-gate field effect transistor
JPS5197385A (en) * 1975-02-21 1976-08-26 Handotaisochino seizohoho
US4105805A (en) * 1976-12-29 1978-08-08 The United States Of America As Represented By The Secretary Of The Army Formation of metal nitride oxide semiconductor (MNOS) by ion implantation of oxygen through a silicon nitride layer
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
US4170492A (en) * 1978-04-18 1979-10-09 Texas Instruments Incorporated Method of selective oxidation in manufacture of semiconductor devices
DE2832388C2 (de) * 1978-07-24 1986-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von MNOS- und MOS-Transistoren in Silizium-Gate-Technologie auf einem Halbleitersubstrat
US4170500A (en) * 1979-01-15 1979-10-09 Fairchild Camera And Instrument Corporation Process for forming field dielectric regions in semiconductor structures without encroaching on device regions
US4266985A (en) * 1979-05-18 1981-05-12 Fujitsu Limited Process for producing a semiconductor device including an ion implantation step in combination with direct thermal nitridation of the silicon substrate
US4272308A (en) * 1979-10-10 1981-06-09 Varshney Ramesh C Method of forming recessed isolation oxide layers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51148362A (en) * 1975-06-04 1976-12-20 Philips Nv Semiconductor device and method of making the same

Also Published As

Publication number Publication date
JPS6235268B2 (2) 1987-07-31
DE3036960A1 (de) 1981-04-02
US4356041A (en) 1982-10-26

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