JPS5665256A - Logical device - Google Patents

Logical device

Info

Publication number
JPS5665256A
JPS5665256A JP14251379A JP14251379A JPS5665256A JP S5665256 A JPS5665256 A JP S5665256A JP 14251379 A JP14251379 A JP 14251379A JP 14251379 A JP14251379 A JP 14251379A JP S5665256 A JPS5665256 A JP S5665256A
Authority
JP
Japan
Prior art keywords
address
execution
counting
time
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14251379A
Other languages
Japanese (ja)
Inventor
Fujio Sekiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14251379A priority Critical patent/JPS5665256A/en
Publication of JPS5665256A publication Critical patent/JPS5665256A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To exactly measure the measured result of the execution time between the commands, the number of command execution steps, etc., by counting a clock pulse of the execution address, and a clock which is generated at every execution, by addition of the pulse counting means.
CONSTITUTION: The execution address of the command to be executed is stored in the address register 10, and the execution address from this register 10 is provided to the address comparator 20. When the address stored in this register 10 has coincided with the start address set by the address designation switch 11, a time counting start signal is sent to the time counting control circuit 30, and when it has coincided with the end address set by the address designation switch 12, a stop signal is sent out to the circuit 30. And after the time counting information counter 40 has been reset, a clock pulse from the clock pulse circuit 50 is counted by the counter 40, and when the circuit 30 has received the stop signal, the counting operation is stopped, at the same time the finish interruption is informed to the upper rank unit, and the execution time between the commands and the number of command execution steps are measured exactly.
COPYRIGHT: (C)1981,JPO&Japio
JP14251379A 1979-11-02 1979-11-02 Logical device Pending JPS5665256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14251379A JPS5665256A (en) 1979-11-02 1979-11-02 Logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14251379A JPS5665256A (en) 1979-11-02 1979-11-02 Logical device

Publications (1)

Publication Number Publication Date
JPS5665256A true JPS5665256A (en) 1981-06-02

Family

ID=15317093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14251379A Pending JPS5665256A (en) 1979-11-02 1979-11-02 Logical device

Country Status (1)

Country Link
JP (1) JPS5665256A (en)

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