JPS5671976A - Preparation method of mos type semiconductor system - Google Patents

Preparation method of mos type semiconductor system

Info

Publication number
JPS5671976A
JPS5671976A JP14980079A JP14980079A JPS5671976A JP S5671976 A JPS5671976 A JP S5671976A JP 14980079 A JP14980079 A JP 14980079A JP 14980079 A JP14980079 A JP 14980079A JP S5671976 A JPS5671976 A JP S5671976A
Authority
JP
Japan
Prior art keywords
small
wiring
gate
preparation
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14980079A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP14980079A priority Critical patent/JPS5671976A/en
Publication of JPS5671976A publication Critical patent/JPS5671976A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a Si gate MOSIC having a small resistance and a small step difference by a method wherein after a poly Si film is selectively oxidized, a silicide of Ni, Pd or Pt is formed and an unreacted metallic film is etched from an oxide film. CONSTITUTION:As in the existing process, a Si gate MOSIC is formed and a poly Si 6 is laminated on the whole surface. A gate wiring part and a connection part with a Si substrate are masked with Si3N4 7. The whole surface except a wiring part 8 and a connection part 9 is oxidized into SiO2. Next thereto, coating is performed with Pt, Pd and Ni, etc. and a sintering is performed to form silicide 10, 11 and unreacted metal on SiO2 is removed by etching. With this constitution, since a wiring resistance is small and step differences are small, there is no anxiety that a disconnection occurs in a wiring of the 2nd layer.
JP14980079A 1979-11-19 1979-11-19 Preparation method of mos type semiconductor system Pending JPS5671976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14980079A JPS5671976A (en) 1979-11-19 1979-11-19 Preparation method of mos type semiconductor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14980079A JPS5671976A (en) 1979-11-19 1979-11-19 Preparation method of mos type semiconductor system

Publications (1)

Publication Number Publication Date
JPS5671976A true JPS5671976A (en) 1981-06-15

Family

ID=15482983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14980079A Pending JPS5671976A (en) 1979-11-19 1979-11-19 Preparation method of mos type semiconductor system

Country Status (1)

Country Link
JP (1) JPS5671976A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052044A (en) * 1983-05-06 1985-03-23 テキサス　インスツルメンツ　インコ−ポレイテツド Method of forming metal silicide
JPS62166568A (en) * 1986-01-20 1987-07-23 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236477A (en) * 1975-09-17 1977-03-19 Philips Nv Method of producing semiconductor device
JPS53139474A (en) * 1977-05-11 1978-12-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236477A (en) * 1975-09-17 1977-03-19 Philips Nv Method of producing semiconductor device
JPS53139474A (en) * 1977-05-11 1978-12-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052044A (en) * 1983-05-06 1985-03-23 テキサス　インスツルメンツ　インコ−ポレイテツド Method of forming metal silicide
JPS62166568A (en) * 1986-01-20 1987-07-23 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof

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