JPS5671981A - Preparation method of semiconductor system - Google Patents
Preparation method of semiconductor systemInfo
- Publication number
- JPS5671981A JPS5671981A JP14981879A JP14981879A JPS5671981A JP S5671981 A JPS5671981 A JP S5671981A JP 14981879 A JP14981879 A JP 14981879A JP 14981879 A JP14981879 A JP 14981879A JP S5671981 A JPS5671981 A JP S5671981A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- walls
- vapored
- fet
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To obtain an FET having a short gate by a method wherein using two resist walls each of which is close to each other and selecting a proper evaporation angle, an electrode is formed. CONSTITUTION:A mesa type N epitaxial layer 7 is installed on a semi-insulating GaAs substrate 6, and resist walls 8, 9 which are extending to a direction are formed making each of them be close to each other. Since the surface is flat and smooth, working of a micro pattern of approximately 1mum can be easily performed. An ohmic metal for the electrode use is vapored from a slant 2 directions and source and drain electrodes 10, 11 are installed. And next thereto, Al and others for the Schottky barrier forming use is vapored to the substrate principal surface from a vertical direction to form a gate electrode 12 on an operation layer 7 between the walls 8 and 9. The resists 8, 9 are removed and a heat processing is performed to form a good ohmic electrode. With this constitution, by means of a self matching, an FET having an extremely short gate length is obtained with a good yield.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981879A JPS5671981A (en) | 1979-11-19 | 1979-11-19 | Preparation method of semiconductor system |
| US06/206,215 US4377899A (en) | 1979-11-19 | 1980-11-12 | Method of manufacturing Schottky field-effect transistors utilizing shadow masking |
| DE19803043289 DE3043289A1 (en) | 1979-11-19 | 1980-11-17 | MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE |
| FR8024416A FR2474761B1 (en) | 1979-11-19 | 1980-11-18 | METHOD FOR MANUFACTURING SCHOTTKY BARRIER FIELD-EFFECT TRANSISTORS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981879A JPS5671981A (en) | 1979-11-19 | 1979-11-19 | Preparation method of semiconductor system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5671981A true JPS5671981A (en) | 1981-06-15 |
| JPS6161549B2 JPS6161549B2 (en) | 1986-12-26 |
Family
ID=15483365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14981879A Granted JPS5671981A (en) | 1979-11-19 | 1979-11-19 | Preparation method of semiconductor system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5671981A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5529952A (en) * | 1994-09-20 | 1996-06-25 | Texas Instruments Incorporated | Method of fabricating lateral resonant tunneling structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS635364A (en) * | 1986-06-25 | 1988-01-11 | Ricoh Co Ltd | Electrophotographic copying device |
-
1979
- 1979-11-19 JP JP14981879A patent/JPS5671981A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5529952A (en) * | 1994-09-20 | 1996-06-25 | Texas Instruments Incorporated | Method of fabricating lateral resonant tunneling structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6161549B2 (en) | 1986-12-26 |
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