JPS5694591A - Failure diagnosis system of buffer memory circuit first-in and first-out - Google Patents

Failure diagnosis system of buffer memory circuit first-in and first-out

Info

Publication number
JPS5694591A
JPS5694591A JP17067179A JP17067179A JPS5694591A JP S5694591 A JPS5694591 A JP S5694591A JP 17067179 A JP17067179 A JP 17067179A JP 17067179 A JP17067179 A JP 17067179A JP S5694591 A JPS5694591 A JP S5694591A
Authority
JP
Japan
Prior art keywords
diagnosis
write
fifo
memory
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17067179A
Other languages
Japanese (ja)
Other versions
JPS6353576B2 (en
Inventor
Junichi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17067179A priority Critical patent/JPS5694591A/en
Publication of JPS5694591A publication Critical patent/JPS5694591A/en
Publication of JPS6353576B2 publication Critical patent/JPS6353576B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To simplify the step of diagnosis and to increase the accuracy of diagnosis, by using the internal signal for FIFO control circuit as the diagnosis data written in the memory, in the FIFO memory circuit failure diagnosis.
CONSTITUTION: After the initial set in the first-in, first-out buffer (FIFO) memory 105, a diagnosis write-in request is made from a diagnosis control circuit 210 with a diagnosis write-in request signal 209. The FIFO control circuit 106 writes in the output of the diagnosis write-in data selection circuit 203 until 4 words with the said diagnosis write-in request into the FIFO memory 105, and the 4 word counter 206 is advanced by one word write-in. This diagnosis write-in data signal 205 of this counter 206 is alternately written in the said FIFO memory 105 for 4 words. The diagnosis control circuit 210 reads out the data written in the FIFO memory 105 and makes failure diagnosis through the collating inspection with the expected value by using a microprocessor.
COPYRIGHT: (C)1981,JPO&Japio
JP17067179A 1979-12-27 1979-12-27 Failure diagnosis system of buffer memory circuit first-in and first-out Granted JPS5694591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17067179A JPS5694591A (en) 1979-12-27 1979-12-27 Failure diagnosis system of buffer memory circuit first-in and first-out

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17067179A JPS5694591A (en) 1979-12-27 1979-12-27 Failure diagnosis system of buffer memory circuit first-in and first-out

Publications (2)

Publication Number Publication Date
JPS5694591A true JPS5694591A (en) 1981-07-31
JPS6353576B2 JPS6353576B2 (en) 1988-10-24

Family

ID=15909211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17067179A Granted JPS5694591A (en) 1979-12-27 1979-12-27 Failure diagnosis system of buffer memory circuit first-in and first-out

Country Status (1)

Country Link
JP (1) JPS5694591A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6715901B2 (en) * 2018-09-21 2020-07-01 株式会社ユニバンス Drive

Also Published As

Publication number Publication date
JPS6353576B2 (en) 1988-10-24

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