JPS6423329A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6423329A
JPS6423329A JP18158387A JP18158387A JPS6423329A JP S6423329 A JPS6423329 A JP S6423329A JP 18158387 A JP18158387 A JP 18158387A JP 18158387 A JP18158387 A JP 18158387A JP S6423329 A JPS6423329 A JP S6423329A
Authority
JP
Japan
Prior art keywords
data
input
time point
ffs
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18158387A
Other languages
Japanese (ja)
Inventor
Minoru Mahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18158387A priority Critical patent/JPS6423329A/en
Publication of JPS6423329A publication Critical patent/JPS6423329A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE:To realize the input of data to another block before the output of data is through by invalidating the first-in/firs-out control after the input/output of data is through with a single clock. CONSTITUTION:The same value is set at both address counters 2 and 3 at a time point T1 and both FFs 7 and 8 are reset. The input of data is unconditionally permitted since the output 111 of the FF 7 is kept reset until a time point T2. A counter 3 is set together with the FFs 7 and 8 at the point T2 and therefore a first-in/first-out FIFO function is validated. The input of data is through at a time point T3 and therefore the FFs 7 and 8 are reset. At this time point the input is completely through with the data on a 1st block, therefore the data may be successively outputted. Thus the FIFO function is invalidated. At a time point T3' an idle address of a memory is used to an address counter 2 and the input of data is started to a 2nd block.
JP18158387A 1987-07-20 1987-07-20 Data processor Pending JPS6423329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18158387A JPS6423329A (en) 1987-07-20 1987-07-20 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18158387A JPS6423329A (en) 1987-07-20 1987-07-20 Data processor

Publications (1)

Publication Number Publication Date
JPS6423329A true JPS6423329A (en) 1989-01-26

Family

ID=16103344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18158387A Pending JPS6423329A (en) 1987-07-20 1987-07-20 Data processor

Country Status (1)

Country Link
JP (1) JPS6423329A (en)

Similar Documents

Publication Publication Date Title
JPS54122043A (en) Electronic computer
JPS56118139A (en) Processor for sampling data
TW260845B (en) Synchronous counter and carry propagation method thereof
JPS5440049A (en) Information process system
JPS54132142A (en) Input/output device identifying system for electronic computer system
JPS54148343A (en) Data transfer control unit
JPS56168254A (en) Advance control system for input/output control unit
JPS5644942A (en) Information processing unit
JPS5394836A (en) Data process system
JPS5759234A (en) Input and output bus device
JPS52106642A (en) Data transfer unit
JPS5654562A (en) Competing circuit
JPS54530A (en) Reference control unit of memory
JPS6431252A (en) Data bus width transformer
JPS55142476A (en) Address conversion system for information processing system
JPS57174723A (en) Bus load controlling system
JPS5351918A (en) Time code fetch unit
JPS5368138A (en) Interrupt priority determining circuit
JPS5694591A (en) Failure diagnosis system of buffer memory circuit first-in and first-out
JPS57125425A (en) System for information transmission
JPS5621228A (en) Date transfer system
JPS57150038A (en) Address designating circuit
JPS54133042A (en) Direct memory access system in multi processor
JPS57169856A (en) Instruction execution system
JPS6451552A (en) Data transfer control system