JPS5710979A - Electrostatic type induction semiconductor device - Google Patents

Electrostatic type induction semiconductor device

Info

Publication number
JPS5710979A
JPS5710979A JP8699680A JP8699680A JPS5710979A JP S5710979 A JPS5710979 A JP S5710979A JP 8699680 A JP8699680 A JP 8699680A JP 8699680 A JP8699680 A JP 8699680A JP S5710979 A JPS5710979 A JP S5710979A
Authority
JP
Japan
Prior art keywords
gate
source
conducted
semiconductor device
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8699680A
Other languages
Japanese (ja)
Inventor
Michio Kotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8699680A priority Critical patent/JPS5710979A/en
Publication of JPS5710979A publication Critical patent/JPS5710979A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To perform the switching of current path by repeatedly and consequtively arranging the first gate regions, the first source regions, and the second gate regions in a line on an N type semiconductor substrate. CONSTITUTION:The first P<+> gate 8, the first N<+> source 9, the second p<+> gate 10, the third P<+> gate 11, the second N<+> source, and the fourth P<+> gate are consecutively arranged on an N type semiconductor substrate 6 having a drain region 7. With the first gate 8 and the second gate 10 kept at zero electric potential, and the third gate 11 and the fourth gate 13 at negative bias, the potential barrier PB at the front of the first source 9 becomes low and the PB at the front of the second source 12 high and the first channel CH1 is conducted and the second channel CH2 is not conducted. With the first gate 8 and the second gate 10 kept at negative voltage and the third gate 11 and the fourth gate 13 at zero electric potential, only the CH2 is conducted.
JP8699680A 1980-06-23 1980-06-23 Electrostatic type induction semiconductor device Pending JPS5710979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8699680A JPS5710979A (en) 1980-06-23 1980-06-23 Electrostatic type induction semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8699680A JPS5710979A (en) 1980-06-23 1980-06-23 Electrostatic type induction semiconductor device

Publications (1)

Publication Number Publication Date
JPS5710979A true JPS5710979A (en) 1982-01-20

Family

ID=13902479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8699680A Pending JPS5710979A (en) 1980-06-23 1980-06-23 Electrostatic type induction semiconductor device

Country Status (1)

Country Link
JP (1) JPS5710979A (en)

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