JPS57152149A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS57152149A
JPS57152149A JP56036340A JP3634081A JPS57152149A JP S57152149 A JPS57152149 A JP S57152149A JP 56036340 A JP56036340 A JP 56036340A JP 3634081 A JP3634081 A JP 3634081A JP S57152149 A JPS57152149 A JP S57152149A
Authority
JP
Japan
Prior art keywords
package
pass capacitor
lsi
pellet
constitute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56036340A
Other languages
Japanese (ja)
Inventor
Masashi Muromachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56036340A priority Critical patent/JPS57152149A/en
Publication of JPS57152149A publication Critical patent/JPS57152149A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/601Capacitive arrangements

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent variation of electric potential of a substrate without increasing the area at an LSI built in with a self sub-bias circuit by a method wherein the dielectric part is provided between the cavity part of a package and the fixed electric power source to constitute a pass capacitor. CONSTITUTION:The dielectric part 2 consisting of a thin dielectric material is provided at the lower part of the cavity part 1 mounted with the LSI pellet. Moreover the conductor part 4 connected to a lead 3 to constitute the fixed electric power source is provided at the lower part thereof. Accordingly at the package thereof, the pass capacitor is formed between the cavity part 1 and the lead 3. At the LSI built in with the self sub-bias circuit, even when an excess current flows in an instant, variation of electric potential of the substrate can be prevented by the pass capacitor thereof, and moreover size of the pellet is not enlarged.
JP56036340A 1981-03-13 1981-03-13 Package for semiconductor device Pending JPS57152149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56036340A JPS57152149A (en) 1981-03-13 1981-03-13 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56036340A JPS57152149A (en) 1981-03-13 1981-03-13 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS57152149A true JPS57152149A (en) 1982-09-20

Family

ID=12467093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56036340A Pending JPS57152149A (en) 1981-03-13 1981-03-13 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS57152149A (en)

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