JPS5772350A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPS5772350A
JPS5772350A JP55148940A JP14894080A JPS5772350A JP S5772350 A JPS5772350 A JP S5772350A JP 55148940 A JP55148940 A JP 55148940A JP 14894080 A JP14894080 A JP 14894080A JP S5772350 A JPS5772350 A JP S5772350A
Authority
JP
Japan
Prior art keywords
electrode layer
electrode
oxide
metal ions
free energy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55148940A
Other languages
Japanese (ja)
Inventor
Iwao Higashinakagaha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55148940A priority Critical patent/JPS5772350A/en
Publication of JPS5772350A publication Critical patent/JPS5772350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To securely hold the surface of a contact hole part of No.1 electrode layer by a method wherein surface treatment is carried out with a standard electrode potential and a fluid including metal ions selected from the viewpoint of free energy forming an oxide. CONSTITUTION:No.2 insulating layer 24 is formed after No.1 electrode layer 23 is deposited via No.1 insulating layer 22 on a semiconductor substrate 21. A contact hole 25 is etched away and its surface is treated, and then No.2 electrode layer 26 which contacts No.1 electrode layer 23 is built. At this moment, its surface treatment is carried out with a fluid that a single electrode potential is noble compared with a material of No.1 electrode layer 23 and yet metal ions of which free energy for forming an oxide is small are included. With this process, good reproducibility and high production yield is gained in connection of No.1 and No.2 electrode layers through the fine hole 25.
JP55148940A 1980-10-24 1980-10-24 Fabrication of semiconductor device Pending JPS5772350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148940A JPS5772350A (en) 1980-10-24 1980-10-24 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148940A JPS5772350A (en) 1980-10-24 1980-10-24 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5772350A true JPS5772350A (en) 1982-05-06

Family

ID=15464057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148940A Pending JPS5772350A (en) 1980-10-24 1980-10-24 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5772350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025418A (en) * 1988-06-23 1990-01-10 Toshiba Corp Surface treatment of metal film and selective deposition of metal film
US7763536B2 (en) 2005-06-21 2010-07-27 Seiko Epson Corporation Method of manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025418A (en) * 1988-06-23 1990-01-10 Toshiba Corp Surface treatment of metal film and selective deposition of metal film
US7763536B2 (en) 2005-06-21 2010-07-27 Seiko Epson Corporation Method of manufacturing a semiconductor device

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