JPS5799763A - Manufacture of lead frame for integrated circuit - Google Patents

Manufacture of lead frame for integrated circuit

Info

Publication number
JPS5799763A
JPS5799763A JP55175608A JP17560880A JPS5799763A JP S5799763 A JPS5799763 A JP S5799763A JP 55175608 A JP55175608 A JP 55175608A JP 17560880 A JP17560880 A JP 17560880A JP S5799763 A JPS5799763 A JP S5799763A
Authority
JP
Japan
Prior art keywords
lead frame
section
onto
aventurine
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55175608A
Other languages
Japanese (ja)
Other versions
JPS6257106B2 (en
Inventor
Kenji Konishi
Mamoru Onda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP55175608A priority Critical patent/JPS5799763A/en
Publication of JPS5799763A publication Critical patent/JPS5799763A/en
Publication of JPS6257106B2 publication Critical patent/JPS6257106B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the lead frame effective for packaging by striately cladding or evaporating Al to a long-sized beltlike base material and removing an excessive section while working the removing section in an aventurine shape. CONSTITUTION:The base material 1 in an alloy of Fe and Ni is fixed to a base 3, a projection 5 for a mask is fast stuck onto a necessary section on a surface, onto the whole surface thereof Al is evaporated, and a device 4 is settled. An etching liquid is sent into 8 a hollow chamber 6, and injected onto an Al surface from a plurality of small holes 7, and Al is removed. Cost is reduced becuase Al is used, contact between the lead frame and a package material is improved and mutual adhesive strength is increased when packaging because aventurine minute unevenness remains on the surface after removing Al, and the infiltration of water can be prevented positively. Contact with solder is also excellent. The surface coated with Al with a complicated shape can be left spottily.
JP55175608A 1980-12-12 1980-12-12 Manufacture of lead frame for integrated circuit Granted JPS5799763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175608A JPS5799763A (en) 1980-12-12 1980-12-12 Manufacture of lead frame for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175608A JPS5799763A (en) 1980-12-12 1980-12-12 Manufacture of lead frame for integrated circuit

Publications (2)

Publication Number Publication Date
JPS5799763A true JPS5799763A (en) 1982-06-21
JPS6257106B2 JPS6257106B2 (en) 1987-11-30

Family

ID=15999063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175608A Granted JPS5799763A (en) 1980-12-12 1980-12-12 Manufacture of lead frame for integrated circuit

Country Status (1)

Country Link
JP (1) JPS5799763A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6372889A (en) * 1986-09-12 1988-04-02 Showa Alum Corp Production of lead frame
JPS63160367A (en) * 1986-12-24 1988-07-04 Hitachi Ltd Plastic-sealed semiconductor device
DE10348715A1 (en) * 2003-10-16 2005-06-16 Infineon Technologies Ag Method for producing and device for improving the adhesion between a plastic and a metal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952976A (en) * 1972-09-22 1974-05-23
JPS553642A (en) * 1978-06-23 1980-01-11 Hitachi Ltd Manufacturing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952976A (en) * 1972-09-22 1974-05-23
JPS553642A (en) * 1978-06-23 1980-01-11 Hitachi Ltd Manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6372889A (en) * 1986-09-12 1988-04-02 Showa Alum Corp Production of lead frame
JPS63160367A (en) * 1986-12-24 1988-07-04 Hitachi Ltd Plastic-sealed semiconductor device
DE10348715A1 (en) * 2003-10-16 2005-06-16 Infineon Technologies Ag Method for producing and device for improving the adhesion between a plastic and a metal
US7732333B2 (en) 2003-10-16 2010-06-08 Infineon Technologies Ag Process for producing and apparatus for improving the bonding between a plastic and a metal

Also Published As

Publication number Publication date
JPS6257106B2 (en) 1987-11-30

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