JPS58107635A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS58107635A
JPS58107635A JP56206552A JP20655281A JPS58107635A JP S58107635 A JPS58107635 A JP S58107635A JP 56206552 A JP56206552 A JP 56206552A JP 20655281 A JP20655281 A JP 20655281A JP S58107635 A JPS58107635 A JP S58107635A
Authority
JP
Japan
Prior art keywords
contact window
window
region
single crystal
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56206552A
Other languages
Japanese (ja)
Other versions
JPH0118577B2 (en
Inventor
Tatsuo Negoro
根来 達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56206552A priority Critical patent/JPS58107635A/en
Publication of JPS58107635A publication Critical patent/JPS58107635A/en
Publication of JPH0118577B2 publication Critical patent/JPH0118577B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification

Landscapes

  • Weting (AREA)

Abstract

PURPOSE:To easily confirm the completion of ething by opening a window only to a single crystal region but also to a supporting region in such a case of etching plurality of single crystal region separately formed on the isolated dielectric material substrate having the supporting region. CONSTITUTION:The Si single crystal island regions 113a, 113b are formed on isolated dielectric materiual substrate 110 where the insulating Si oxide films 112a, 112b are formed in a supporring region 111 consisting of the poly crystal Si, and for example vertical transistor and diode are formed on the island regions 113a, 113b. After the surface is covered with an oxide film, contact windows, for example, the collector contact window 114, emitter contact window 115, base contact window 116, cathode contact window 117, anode contact window 118 are finally provided thereon. At this time, a window 119 for checking the end of ethcing for oxide film is provided also on the polycrystal line supporting region 111. Thereby, the end of etching can be checked easily and overetching can also be provented.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特に誘電体分離
基板を用いた集積回路装置の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an integrated circuit device using a dielectric isolation substrate.

従来の誘電体分離基板への拡散に際しては、熱酸化で成
長したシリコン酸化膜をマスクとして単結晶シリコンに
選択拡散を行う方法を採っている。
When diffusing into a conventional dielectric isolation substrate, a method is adopted in which selective diffusion is performed into single crystal silicon using a silicon oxide film grown by thermal oxidation as a mask.

仁の場合、フォトリソグラフィ工程における酸化膜エツ
チングの終了を、金J4顕微鏡を用いて単結晶シリコン
上の窓あけの色で判断していた。しかしながら、これで
はエツチング状態を正確に観察できず、エツチング不足
やエツチング過剰をしばしばひき起す等の問題点が発生
していた。
In the case of Jin, the completion of oxide film etching in the photolithography process was determined by the color of the opening on the single crystal silicon using a Gold J4 microscope. However, with this method, it is not possible to accurately observe the etching state, resulting in problems such as insufficient etching or excessive etching.

本発明の目的は、このような問題点を解決した半導体装
置の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that solves these problems.

本発明は、回路素子が形成される複数の単結晶領域を互
いに電気的に絶縁分離しつつ支持する支持体領域からな
る誘電体分離基板へのフォトリングラフィf工程を備え
た半導体装置において、前記単結晶領域だけでなく前記
支持体領域にも窓あけを行なう工程を有することを特徴
とする半導体装置の製造方法にある。
The present invention provides a semiconductor device comprising a photolithography f process on a dielectric isolation substrate comprising a support region that supports a plurality of single crystal regions on which circuit elements are formed while electrically insulating and separating them from each other. The method of manufacturing a semiconductor device is characterized by comprising the step of forming a window not only in the single crystal region but also in the support region.

次に図面を参照して、本発明を説明する。Next, the present invention will be explained with reference to the drawings.

第1図は従来の製造方法を説明するための誘電体分離基
板の平面図である。この誘電体分離基板10は、シリコ
ン多結晶支持領域11中に絶縁性のシリコン酸化膜12
1,12bを介してそれぞれシリコン単結晶島領域13
a%13bが並んで埋設されているウシリコン単結晶島
領域1311,13bは互いに同一導電型であっても、
異った導電型であって4かまわない。シリコン単結晶島
領域131には、縦型トランジスタが拡散されておシ、
他のシリコン単結晶島領域13bKはダイオードが拡散
され、コンタクトの窓あけを行なったときの状態を示し
ている。縦型トランジスタにはコレクタコンタクト窓1
4、エミッタコンタクト窓1 s sベースコンタクト
窓16の領域が設けられ、ダイオードには、カソードコ
ンタクト窓177ノードコンタクト窓の領域が設けられ
る。従来の方法による酸化膜エツチングの終了の判断は
、これらのコンタクト窓に酸化膜が残っているかどうか
を金属顕微鏡によシ観察して判断していた。
FIG. 1 is a plan view of a dielectric isolation substrate for explaining a conventional manufacturing method. This dielectric isolation substrate 10 has an insulating silicon oxide film 12 in a silicon polycrystalline support region 11.
1 and 12b through silicon single crystal island regions 13, respectively.
Even though the silicon single crystal island regions 1311 and 13b buried side by side with a% 13b are of the same conductivity type,
There may be 4 different conductivity types. A vertical transistor is diffused in the silicon single crystal island region 131.
The other silicon single crystal island region 13bK shows a state in which a diode is diffused and a contact window is opened. Collector contact window 1 for vertical transistors
4. Emitter contact window 1 s s Base contact window 16 area is provided, the diode is provided with cathode contact window 177 node contact window area. In the conventional method, the completion of oxide film etching was determined by observing with a metallurgical microscope whether or not an oxide film remained on these contact windows.

第2図は本発明の製造方法を説明するための誘電体分離
基板の平面図である。同図において、この誘電体分離基
板110は、シリコン多結晶支持領域111中に絶縁性
のシリコン酸化膜112J1,112bを介してシリコ
ン単結晶島領域113a、113bが設けられている。
FIG. 2 is a plan view of a dielectric isolation substrate for explaining the manufacturing method of the present invention. In the figure, in this dielectric isolation substrate 110, silicon single crystal island regions 113a and 113b are provided in a silicon polycrystal support region 111 via insulating silicon oxide films 112J1 and 112b.

シリコン単結晶島領域11351には縦型トランジスタ
が拡散されておシ、他のシリコン単結晶島領域113b
にはダイオードが拡散され、コンタクトの窓あけを行っ
たときの状態を示している。
Vertical transistors are diffused in the silicon single crystal island region 11351, and the other silicon single crystal island region 113b
shows the state when the diode is diffused and the contact window is opened.

縦型トランジスタには、コレクタコンタクト窓114、
エミッタコンタクト窓115、ベースコンタクト窓11
6の領域が設けられ、ダイオード117にはカソードコ
ンタクト窓117、アノードコンタクト窓118の領域
が設けられる。同時に、多結晶支持領域111上に酸化
膜エツチング終了チェック用窓119が設けられる。こ
のチェック用窓119を設けることKより、シリコン単
結晶島領域113a、113bのコレクタ、エミッタペ
ース領域等のコンタクト窓あけのエツチング終了の確認
が非常によく制御できるようになる。
The vertical transistor has a collector contact window 114,
Emitter contact window 115, base contact window 11
The diode 117 is provided with a cathode contact window 117 and an anode contact window 118. At the same time, a window 119 for checking the completion of oxide film etching is provided on the polycrystalline support region 111. By providing this check window 119, confirmation of the completion of etching for forming contact windows in the collector and emitter space regions of the silicon single crystal island regions 113a and 113b can be very well controlled.

即ち、多結晶シリコンからなる支持体領域と、単結晶シ
リコンからなる素子形成領域とを同一条件で熱酸化した
部分に、フォトリソグラフィにより、それぞれ窓あけし
て7ツ化アンモニ為ウムと7ツ酸との混合液で酸化膜エ
ツチングを行なうと、多結晶シリコン上の熱酸化膜には
多結晶のすき間に酸化膜が成長している為、単結晶上の
熱酸化膜をエツチングするよりもわずかにエツチング時
間を要し、しかも多結晶の模様が金属顕微鏡ではっきり
と観察できる。この多結晶の酸化膜よる模様がなくなっ
たとき単結晶シリコン上の酸化膜は完全に除去され、し
かもエツチング過剰は実質的に生じていない。
That is, a support region made of polycrystalline silicon and an element formation region made of single-crystal silicon were thermally oxidized under the same conditions, and a window was opened by photolithography, and ammonium heptatide and heptazate were respectively formed. When etching an oxide film with a mixed solution of Etching takes time, and the polycrystalline pattern can be clearly observed with a metallurgical microscope. When the pattern caused by the polycrystalline oxide film disappears, the oxide film on the single crystal silicon is completely removed, and there is substantially no excessive etching.

従って、本発明によれば、酸化膜エツチングの終止点の
観察が非常に容易となるため、均一な特性で信頼性の高
い半導体装置を製造することができる。
Therefore, according to the present invention, it is very easy to observe the end point of oxide film etching, so it is possible to manufacture a highly reliable semiconductor device with uniform characteristics.

上記実施例はコンタクトの窓あけについて説明。The above embodiment describes the opening of the contact window.

したが、熱酸化後であれば、選択拡散前の全てのフォト
リソグラフィ工程で、本発明が適用できること勿論であ
る。
However, it goes without saying that the present invention can be applied to all photolithography steps after thermal oxidation and before selective diffusion.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の誘電体分離基板を部分的に
示す平面図、第2図は本発明の一実施例を説明する半導
体装置の誘電体分離基板を部分的に示す平面図である。 同図において、 10%110・・・・・・誘電体分離基板、1.1,1
1.1・・・・・・シリコン多結晶支持領域、12a、
 12b1112a、 112b・・−−−−シリコン
酸化膜、13a、 13b、 113Jl、 113b
・・・・・・シリコン単結晶島領域、14,114・・
・・・・コレクタコンタクト窓515sl15・・・・
・・エミッタコンタクト窓、16.116・・・・・・
ベースコンタクト窓、17%117・・・・・・カソー
ドコンタクト窓、18,118・・・・・・アノードコ
ンタクト窓、119・・・・・・酸化膜エツチング終了
チェック用窓。
FIG. 1 is a plan view partially showing a dielectric isolation substrate of a conventional semiconductor device, and FIG. 2 is a plan view partially showing a dielectric isolation substrate of a semiconductor device illustrating an embodiment of the present invention. . In the same figure, 10%110...dielectric isolation substrate, 1.1,1
1.1...Silicon polycrystalline support region, 12a,
12b1112a, 112b...---Silicon oxide film, 13a, 13b, 113Jl, 113b
...Silicon single crystal island region, 14,114...
...Collector contact window 515sl15...
...Emitter contact window, 16.116...
Base contact window, 17% 117... Cathode contact window, 18, 118... Anode contact window, 119... Window for checking completion of oxide film etching.

Claims (1)

【特許請求の範囲】[Claims] 回路素子が形成される複数の単結晶領域を互いに電気的
に絶縁分離しつつ支持する支持体領域からなる誘電体分
離基板へのフォトリングラフィ工程を備えた半導体装置
の製造方法において、前記単結晶領域だけでなく前記支
持体領域にも窓あけを行う工程を有することを特徴とす
る半導体装置の製造方法。
In a method of manufacturing a semiconductor device comprising a photolithography process on a dielectric isolation substrate comprising a support region that supports a plurality of single crystal regions on which circuit elements are formed while electrically insulating and separating them from each other, A method for manufacturing a semiconductor device, comprising the step of forming a window not only in the region but also in the support region.
JP56206552A 1981-12-21 1981-12-21 Preparation of semiconductor device Granted JPS58107635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56206552A JPS58107635A (en) 1981-12-21 1981-12-21 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56206552A JPS58107635A (en) 1981-12-21 1981-12-21 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58107635A true JPS58107635A (en) 1983-06-27
JPH0118577B2 JPH0118577B2 (en) 1989-04-06

Family

ID=16525271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56206552A Granted JPS58107635A (en) 1981-12-21 1981-12-21 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58107635A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165320A (en) * 1980-05-23 1981-12-18 Sanyo Electric Co Ltd Formation of multilayer electrodes of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165320A (en) * 1980-05-23 1981-12-18 Sanyo Electric Co Ltd Formation of multilayer electrodes of semiconductor device

Also Published As

Publication number Publication date
JPH0118577B2 (en) 1989-04-06

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