JPS5839059U - リ−ドフレ−ム - Google Patents

リ−ドフレ−ム

Info

Publication number
JPS5839059U
JPS5839059U JP1981133952U JP13395281U JPS5839059U JP S5839059 U JPS5839059 U JP S5839059U JP 1981133952 U JP1981133952 U JP 1981133952U JP 13395281 U JP13395281 U JP 13395281U JP S5839059 U JPS5839059 U JP S5839059U
Authority
JP
Japan
Prior art keywords
island
lead frame
hanging
sections
hanging pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981133952U
Other languages
English (en)
Inventor
南部　哲司
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1981133952U priority Critical patent/JPS5839059U/ja
Publication of JPS5839059U publication Critical patent/JPS5839059U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来例の平面図、第２図は半導体素子のアイラ
ンド部へのマウント状態を示す側断面図、第３図は本案
の一実施例を示す平面図、第４図は半導体素子のアイラ
ンド部へのマウント状態を示す側断面図、第５図は半導
体装置の横断面図である。 図中、１は枠部分、２はタイバー、３はアイランド部、
４は吊りピン、５は中間接続部、６〜９はリードである
。

Claims (1)

    【実用新案登録請求の範囲】
  1. 平行に延びる枠部分を一定の間隔にて連結したタインく
    一間にアイランド部を、枠部分より延びる吊りピンにて
    一体的に固定すると共に、タイバーよりアイランド部に
    向けて複数のリードを延在させたものにおいて、上記ア
    イランド部と吊りピンとの固定部分にアイランド部より
    巾が狭くかつ吊りピンより充分に巾の広い中間接続部を
    介在させたことを特徴とするリードフレーム。
JP1981133952U 1981-09-09 1981-09-09 リ−ドフレ−ム Pending JPS5839059U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981133952U JPS5839059U (ja) 1981-09-09 1981-09-09 リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981133952U JPS5839059U (ja) 1981-09-09 1981-09-09 リ−ドフレ−ム

Publications (1)

Publication Number Publication Date
JPS5839059U true JPS5839059U (ja) 1983-03-14

Family

ID=29927395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981133952U Pending JPS5839059U (ja) 1981-09-09 1981-09-09 リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS5839059U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214448A (ja) * 1985-07-12 1987-01-23 Hitachi Ltd 半導体装置用リ−ドフレ−ム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214448A (ja) * 1985-07-12 1987-01-23 Hitachi Ltd 半導体装置用リ−ドフレ−ム

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