JPS5840614Y2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5840614Y2
JPS5840614Y2 JP1981004300U JP430081U JPS5840614Y2 JP S5840614 Y2 JPS5840614 Y2 JP S5840614Y2 JP 1981004300 U JP1981004300 U JP 1981004300U JP 430081 U JP430081 U JP 430081U JP S5840614 Y2 JPS5840614 Y2 JP S5840614Y2
Authority
JP
Japan
Prior art keywords
wire bonding
circuit element
wire
external lead
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981004300U
Other languages
English (en)
Japanese (ja)
Other versions
JPS56167549U (2
Inventor
健一 近藤
謙二郎 八木
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP1981004300U priority Critical patent/JPS5840614Y2/ja
Publication of JPS56167549U publication Critical patent/JPS56167549U/ja
Application granted granted Critical
Publication of JPS5840614Y2 publication Critical patent/JPS5840614Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1981004300U 1981-01-16 1981-01-16 半導体装置 Expired JPS5840614Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981004300U JPS5840614Y2 (ja) 1981-01-16 1981-01-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981004300U JPS5840614Y2 (ja) 1981-01-16 1981-01-16 半導体装置

Publications (2)

Publication Number Publication Date
JPS56167549U JPS56167549U (2) 1981-12-11
JPS5840614Y2 true JPS5840614Y2 (ja) 1983-09-13

Family

ID=29600988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981004300U Expired JPS5840614Y2 (ja) 1981-01-16 1981-01-16 半導体装置

Country Status (1)

Country Link
JP (1) JPS5840614Y2 (2)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182858A (ja) * 1982-04-21 1983-10-25 Nec Corp リ−ドフレ−ム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN=1967 *

Also Published As

Publication number Publication date
JPS56167549U (2) 1981-12-11

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