JPS5854423A - 制御システムの偽応答方式 - Google Patents

制御システムの偽応答方式

Info

Publication number
JPS5854423A
JPS5854423A JP56152602A JP15260281A JPS5854423A JP S5854423 A JPS5854423 A JP S5854423A JP 56152602 A JP56152602 A JP 56152602A JP 15260281 A JP15260281 A JP 15260281A JP S5854423 A JPS5854423 A JP S5854423A
Authority
JP
Japan
Prior art keywords
false response
block
cpu1
cpu
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56152602A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6213701B2 (fr
Inventor
Kenji Hiramine
平嶺　建二
Reijiro Aoki
青木　礼次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP56152602A priority Critical patent/JPS5854423A/ja
Publication of JPS5854423A publication Critical patent/JPS5854423A/ja
Publication of JPS6213701B2 publication Critical patent/JPS6213701B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Debugging And Monitoring (AREA)
JP56152602A 1981-09-26 1981-09-26 制御システムの偽応答方式 Granted JPS5854423A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56152602A JPS5854423A (ja) 1981-09-26 1981-09-26 制御システムの偽応答方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56152602A JPS5854423A (ja) 1981-09-26 1981-09-26 制御システムの偽応答方式

Publications (2)

Publication Number Publication Date
JPS5854423A true JPS5854423A (ja) 1983-03-31
JPS6213701B2 JPS6213701B2 (fr) 1987-03-28

Family

ID=15543993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56152602A Granted JPS5854423A (ja) 1981-09-26 1981-09-26 制御システムの偽応答方式

Country Status (1)

Country Link
JP (1) JPS5854423A (fr)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5789124A (en) * 1980-11-21 1982-06-03 Fujitsu Ltd Interface converter of information process system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5789124A (en) * 1980-11-21 1982-06-03 Fujitsu Ltd Interface converter of information process system

Also Published As

Publication number Publication date
JPS6213701B2 (fr) 1987-03-28

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