JPS586595A - 記憶装置制御方式 - Google Patents

記憶装置制御方式

Info

Publication number
JPS586595A
JPS586595A JP56102933A JP10293381A JPS586595A JP S586595 A JPS586595 A JP S586595A JP 56102933 A JP56102933 A JP 56102933A JP 10293381 A JP10293381 A JP 10293381A JP S586595 A JPS586595 A JP S586595A
Authority
JP
Japan
Prior art keywords
signal
error
cpu
storage device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56102933A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6131498B2 (2
Inventor
Shuji Ito
修二 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56102933A priority Critical patent/JPS586595A/ja
Publication of JPS586595A publication Critical patent/JPS586595A/ja
Publication of JPS6131498B2 publication Critical patent/JPS6131498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP56102933A 1981-06-30 1981-06-30 記憶装置制御方式 Granted JPS586595A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56102933A JPS586595A (ja) 1981-06-30 1981-06-30 記憶装置制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56102933A JPS586595A (ja) 1981-06-30 1981-06-30 記憶装置制御方式

Publications (2)

Publication Number Publication Date
JPS586595A true JPS586595A (ja) 1983-01-14
JPS6131498B2 JPS6131498B2 (2) 1986-07-21

Family

ID=14340638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56102933A Granted JPS586595A (ja) 1981-06-30 1981-06-30 記憶装置制御方式

Country Status (1)

Country Link
JP (1) JPS586595A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07325762A (ja) * 1994-06-02 1995-12-12 Nec Corp 冗長メモリの制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07325762A (ja) * 1994-06-02 1995-12-12 Nec Corp 冗長メモリの制御方式

Also Published As

Publication number Publication date
JPS6131498B2 (2) 1986-07-21

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