JPS5892763U - 厚膜多層基板 - Google Patents

厚膜多層基板

Info

Publication number
JPS5892763U
JPS5892763U JP1981187105U JP18710581U JPS5892763U JP S5892763 U JPS5892763 U JP S5892763U JP 1981187105 U JP1981187105 U JP 1981187105U JP 18710581 U JP18710581 U JP 18710581U JP S5892763 U JPS5892763 U JP S5892763U
Authority
JP
Japan
Prior art keywords
conductor group
thick film
film multilayer
multilayer substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981187105U
Other languages
English (en)
Inventor
泰男 井口
柴田　勲夫
荒尾　義範
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1981187105U priority Critical patent/JPS5892763U/ja
Publication of JPS5892763U publication Critical patent/JPS5892763U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図と第２図は従来の厚膜多層基板の断面図、第３図
は本考案による厚膜多層基板の断面図、第４図は本考案
による厚膜多層基板にＩＣチップを搭載した図を示す。 １．１１．２１・・・・・・セラミック基板、２，１２
゜２２・・・・・・第１の導体群、３．　１３．　２３
・・・・・・中間絶縁層、４．　１４．　２４・・・・
・・第２の導体群、１５・・・・・・絶縁ガラス、２５
・・・・・・ＩＣチップ、２６・・・・・・ボンディン
グワイヤー。

Claims (1)

    【実用新案登録請求の範囲】
  1. 平担な表面を有する絶縁基板と、その表面に所定の間隔
    で平行に配置される第１の導体群と、該第１の導体群を
    薄く覆う中間絶縁層と、該中間絶縁層の上に前記第１の
    導体群と平行に前記所定の間隔で第１の導体群に対し半
    格子だけずらして配置される第２の導体群とを有するこ
    とを特徴とする厚膜多層基板。
JP1981187105U 1981-12-17 1981-12-17 厚膜多層基板 Pending JPS5892763U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981187105U JPS5892763U (ja) 1981-12-17 1981-12-17 厚膜多層基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981187105U JPS5892763U (ja) 1981-12-17 1981-12-17 厚膜多層基板

Publications (1)

Publication Number Publication Date
JPS5892763U true JPS5892763U (ja) 1983-06-23

Family

ID=29989630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981187105U Pending JPS5892763U (ja) 1981-12-17 1981-12-17 厚膜多層基板

Country Status (1)

Country Link
JP (1) JPS5892763U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134874A (en) * 1975-05-19 1976-11-22 Nippon Electric Co Method of manufacturing thick film multilayered wiring substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134874A (en) * 1975-05-19 1976-11-22 Nippon Electric Co Method of manufacturing thick film multilayered wiring substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

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