JPS6076046U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6076046U
JPS6076046U JP1983166949U JP16694983U JPS6076046U JP S6076046 U JPS6076046 U JP S6076046U JP 1983166949 U JP1983166949 U JP 1983166949U JP 16694983 U JP16694983 U JP 16694983U JP S6076046 U JPS6076046 U JP S6076046U
Authority
JP
Japan
Prior art keywords
metal
metal wiring
semiconductor device
external terminal
semiconductor equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983166949U
Other languages
English (en)
Inventor
成川　孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1983166949U priority Critical patent/JPS6076046U/ja
Publication of JPS6076046U publication Critical patent/JPS6076046U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/641—Dispositions of strap connectors
    • H10W72/646—Dispositions of strap connectors the connected ends being on auxiliary connecting means on bond pads, e.g. on a bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/691—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図、第２図は従来の半導体装置及びその接続構造を
示す断面図、第３図は第１図、第２図の半導体装置の平
面図、第４図は本考案の一実施例の平面図、第５図は第
４図の一実施例及びその接続構造を示す断面図である。 １．１１・・・・・・半導体チップ、２，１２，１２’
・・・・・・金属電極、３，１３・・・・・・金属配線
、４，１４・・・・・・リードフレーム、５，１５・・
・・・・リードフレーム先端部、６，１６・・・・・・
実装プリント板金属配線部、７，１７・・・・・・絶縁
膜、訃・・・・・突起部、９・・・・・・もり上げ部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板に形成された半導体素子間を金属配線で結び
    、該金属配線を外部端子へ導出する為の金属電極を有す
    る半導体装置において、金属配線゛及び又は金属電極を
    絶縁膜を介して多層化し少なくとも表面層に複数金属電
    極を導出し、該複数の金属電極は相互に一定間隔を保持
    し、かつ最大限面積と一定厚さで形成され、該金属電極
    が外部端子に直接接続されるようになされていることを
    特徴とする半導体装置。
JP1983166949U 1983-10-28 1983-10-28 半導体装置 Pending JPS6076046U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983166949U JPS6076046U (ja) 1983-10-28 1983-10-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983166949U JPS6076046U (ja) 1983-10-28 1983-10-28 半導体装置

Publications (1)

Publication Number Publication Date
JPS6076046U true JPS6076046U (ja) 1985-05-28

Family

ID=30365371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983166949U Pending JPS6076046U (ja) 1983-10-28 1983-10-28 半導体装置

Country Status (1)

Country Link
JP (1) JPS6076046U (ja)

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