JPS59103455U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59103455U
JPS59103455U JP1982199638U JP19963882U JPS59103455U JP S59103455 U JPS59103455 U JP S59103455U JP 1982199638 U JP1982199638 U JP 1982199638U JP 19963882 U JP19963882 U JP 19963882U JP S59103455 U JPS59103455 U JP S59103455U
Authority
JP
Japan
Prior art keywords
power supply
semiconductor equipment
supply pad
integrated circuit
showing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982199638U
Other languages
English (en)
Other versions
JPH0124933Y2 (ja
Inventor
光久 清水
酒井　敏昭
名和田　一正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1982199638U priority Critical patent/JPS59103455U/ja
Publication of JPS59103455U publication Critical patent/JPS59103455U/ja
Application granted granted Critical
Publication of JPH0124933Y2 publication Critical patent/JPH0124933Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は大規模集積回路を収容した半導体装置の一例を
示す断面図、第２図の４９０図は半導チップに形成され
るマスクスライス方式のパターン例を示す図であリイは
平面図、口はイの斜線で示すパターン部拡大図、第３図
は本考案の半導体チップパターン構成の一実施例を示す
平面図、第４図は本考案の半導体チップをパッケージに
収容して各パッド間をワイヤボンデング接続する要部平
面図、第５図は本考案の一実施例である電源パッド部を
示す拡大図、第６図、第７図は電源パッド部におけるワ
イヤ接続を示すための図であり、第６図はＡ−Ａ’　、
第７図はＢ−Ｂ’部を示す断面図　　。 である。 図中１１・・・・・・半導体チップ、１２・・・・・・
信号パッド、１３．１５・・・・・・電源パッド、１４
・・・・・・パターン導体、１６・・・・・・セラミッ
ク基板、１７・・・・・・ワイヤ、１８・・・・・・パ
ッド（メタライス）、１９・・・・・・二酸化シリコン
膜、２０．２１・・・・・・アルミニウム膜、　　　′
２２．２３・・・・・・絶縁膜。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体集積回路チップの素子周辺部に形成された第１の
    電源パッドと該第１の電源パッドに接続され、集積回路
    に動作電圧を供給する電源線上に形成された第２の電源
    パッドとを有することを特徴とする半導体装置。
JP1982199638U 1982-12-28 1982-12-28 半導体装置 Granted JPS59103455U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982199638U JPS59103455U (ja) 1982-12-28 1982-12-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982199638U JPS59103455U (ja) 1982-12-28 1982-12-28 半導体装置

Publications (2)

Publication Number Publication Date
JPS59103455U true JPS59103455U (ja) 1984-07-12
JPH0124933Y2 JPH0124933Y2 (ja) 1989-07-27

Family

ID=30425164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982199638U Granted JPS59103455U (ja) 1982-12-28 1982-12-28 半導体装置

Country Status (1)

Country Link
JP (1) JPS59103455U (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125085A (ja) * 1974-06-26 1976-03-01 Ibm
JPS53140983A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Semiconductor integrated circuit
JPS5694041U (ja) * 1979-12-20 1981-07-25
JPS59100550A (ja) * 1982-11-30 1984-06-09 Mitsubishi Electric Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125085A (ja) * 1974-06-26 1976-03-01 Ibm
JPS53140983A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Semiconductor integrated circuit
JPS5694041U (ja) * 1979-12-20 1981-07-25
JPS59100550A (ja) * 1982-11-30 1984-06-09 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH0124933Y2 (ja) 1989-07-27

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