JPS59201415A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain super-fine gate electrode width by forming the source and drain by ion implantation after providing a resist mask and etching the gate electrode material, and then executing shallow ion implantation from the resist with the narrow gate electrode used as the mask. CONSTITUTION:A resist mask 45 is formed on a poly-Si 44 on an oxide thin film 43 of a Si substrate 41 and then it is etched. Thereby, width of layer 44 is made narrower than that of mask 45 and the source layer 46 and drain layer 47 are formed by ion implantation. With the poly-Si layer 44 used as the mask, shallower ion implantation is carried out in order to form the regions 461, 471 in the channel side. The regions 461, 471 less spread in lateral and elongation of deletion layers 61, 62 is also small and therefore short channel effect can be neglected. According to this structure, an MOSFET of super fine gate width where the short channel effect can be neglected can be obtained stably with each control for threshold level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device such as a self-adjusted gate transistor in which source and drain regions are formed using a gate electrode as a mask. .

[Technical background of the invention]

Conventionally, MOS (Metal Oxide Sem
1 conductor) LSI (Large 5ca
integrated circuit), for example, a polycrystalline silicon gate MOS transistor (-
In this case, the entire source and drain regions are removed using the polycrystalline silicon used as the gate electrode as a mask. With reference to FIGS. 1 and 2, a method for manufacturing a polycrystalline silicon gate MOS transistor will be described as a so-called cell align date transistor -flj. Figure 1 shows one MOS in MOS LSI +-
) Planar view showing the transistor pattern, Figure 2 (AJ~
(C1 is A, -A of the pattern shown in the first factor, respectively)
' shows a cross section along the line. Figure 1 (2)
11 is a source head, 12 is a drain region, and 13 is a dirt region. First, in Figure 2 (Al-2, 21 is a semiconductor substrate, and the Saone sushi area 1 on this semiconductor substrate 21 is
Drain region 12. A thick oxide film 22 is previously formed in the regions other than the dirt region 13, and the source region 11.
Drain region g1z.

The head region 13 of the skeleton is also formed with a thin oxide +1jλ23. Reference numeral 24 denotes a polycrystalline silicon layer which becomes a dirt electrode formed on the thin oxide film 23 (-).

Next, as shown in FIG. 2B, ion implantation is performed using the polycrystalline silicon layer 24 as a mask (-).

In this case, ion implantation (the sulfur injected from two sources is applied to the thick oxide film 22 and the polycrystalline silicon layer 22).
Since the laser beam is blocked by the laser beam, it does not enter the lower part thereof, and therefore, it is implanted into the semi-funeral substrate 21 in other areas. In this way, the source region 1 is shown in FIG. 2 (CJ).
1 and the drain region are shaped like 1.

[Problems with background technology]

As described above, in the manufacturing method in which the source region 11 and the drain 12 are formed using the gate' magnetic pole of the child crystal silicon i+ blind 24 as a mask, as the microfabrication of integrated circuits progresses, the polycrystalline silicon layer 24 If the width of the transistor becomes very small (-), a short channel effect will occur in the transistor.

Since such a short channel effect has the effect of lowering the threshold value of a transistor, there is a drawback in that it becomes extremely difficult to control the threshold value in the manufacture of enhancement type transistors, for example. Therefore, the short channel effect ′fr,
Unless there is some means to prevent this, even if microfabrication technology for integrated circuits advances, the width of the polycrystalline silicon layer 24, which becomes greasy, cannot be made smaller, resulting in a corresponding increase in the size of the polycrystalline silicon layer.

The following two factors can be cited as causes for the short channel effect described above.

(1) As shown in FIG.
Channel length becomes smaller.

(2) As shown in FIG. 3, depletion layers 31 and 32 extend from the source region 11 and drain region 12, reducing the effective channel length.

As a countermeasure to prevent the above-mentioned short channel effect from occurring.

(11) A method of suppressing the lateral spread of the source region 1 and the drain region J2 by reducing the depth of the diffusion layer that becomes the source region 11 and the drain region 12.

(2) A method of reducing the extent of depletion, 91, and 32 by including ions of low and low occupancy in the semiconductor substrate.

I got angry.

However, how to counter the first item mentioned above (7-): In the IU, the diffusion υ must be reduced, and as a result, the resistance of 12 in the source region 11 and the drain region 1 is extremely large. It had the disadvantage of being large.

Furthermore (-1 2nd iJA countermeasures (2 left, Depletion Jr!
I: Ion implantation to suppress the spread of xr32 completely changes the threshold of the transistor (- ion implantation process jll, k k
It's very difficult to decide.

As mentioned above, the MOS of C2 conventional self line dart
) In the case of a runnostar having a dirt electrode of a larva whose price is the same, it is difficult to control the threshold value due to the short channel effect, which has the disadvantage of lowering the yield of LSI.

[Purpose of the invention]

This invention was made in view of the above points.

The purpose is to eliminate the short channel effect that occurs in MOS transistors having dart electrodes with a fine width, and to provide a method for manufacturing a semiconductor device that allows easy microfabrication.

[Summary of the invention]

In the present invention, when forming the source and drain regions of a self-line gate MOS transistor, ion implantation is performed in two steps.

First, using the resist with the pattern for the gate electrode as a mask, etch the entire lower layer of the rennost layer (-) to form a dirt electrode, and then perform the first ion implantation (from '- to the entire source and drain region). Next, a dirt electrode (with a width smaller than the width of the resist formed 1 m below the removed resist) is masked) - and then the source and drain electrodes already formed by the second ion implantation are removed. The source and drain regions are formed shallower than the source and drain regions.

[Embodiments of the invention]

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to Figure 1. I will clarify.

In the fourth section, 41 is a semiconductor substrate.

An oxide film 42 is previously formed on the semiconductor substrate 41 except for the regions where the source region, drain region, and goat region are to be formed.

A thin oxide film 43 is formed in a region where a drain region and a dirt region are to be formed. Also.

44 is a polycrystalline silicon layer ζ'' on the thin oxide film 43, which will become a dirt electrode to be formed; 45 is a resist that will serve as a mask when etching the polycrystalline silicon 44; After etching the crystalline silicon layer 44, the width of the polycrystalline silicon layer 44 becomes smaller than the width of the renost 45.
5. Perform the first ion implantation to completely form the source and drain regions using a full mask. Therefore, the lower part (2) is not included, but in other areas, the semiconductor substrate 4 (-) is implanted.Next, the appearance after removing the resist 45 is shown in Figure 4 (B). Keep it.Figure 4C
As shown in B+ (2) the source region @46 and the drain region 47 are formed by the above ion implantation.
As shown in FIG. The depth of the second ion implantation is made shallower than the depth of the first ion implantation.As a result, as shown in FIG. .471 will be formed shallowly.

Next, FIG. 5 shows an enlarged view of FIG. 4(D). As shown in FIG. 5, the implantation depth of the second ion implantation is shallower than the implantation depth of the first ion implantation. The lateral extent of 461 and 471 is small.

The elongation of the depletion layers 6] and 62 is small. For this reason.

The short channel effect is very (2) small and can be uncut (-).

Note that the dart electrode may of course be made of aluminum.

In the above example (2), the second ion implantation process (-
There is no need for a mask for patterning the entire polycrystalline silicon layer 44 used as a mask.

The number of masks will not increase compared to before. In addition, since the depletion layer has a small elongation, the threshold value can be easily controlled (it can be done in two ways).

Further, since the first ion implantation is performed deeply and the second ion implantation is performed shallowly, the resistance of the source and drain regions does not become quotient.

〔Effect of the invention〕

As detailed above, this invention (-) does not require ion implantation to suppress the spread of the depletion layer even in a MOS transistor with a very small gate polarity, and therefore it is easy to control the threshold value. As a result, it is possible to fabricate transistors with no (or less) short channel effects.
Since it is possible to manufacture all the stable transistors, high integration is possible - LSI manufacturing (2 is very effective manufacturing method).

[Brief explanation of the drawing]

Figure 1 is a plan view showing the pattern of an A40S) transistor, Figure 2 is a diagram showing a method of manufacturing a conventional MOS transistor, Figure 3 is a cross-sectional view of a conventional MOS transistor. One Embodiment (-Semiconductor device according to the present invention) Fig. 5 shows a semiconductor device according to one embodiment of the present invention. 4) Semiconductor substrate, 44... Ax crystal silicon layer. 45...Resist, 46...Source region, 47-
...Drain region.

Claims (1)

[Claims] A process of etching the entire Lennost mask with a pattern of ``dirt pattern; and a step of forming the entire drain region, and a step of removing the resist, and a step of injecting ions L and L using a dirt electrode having a width smaller than the width of the resist formed under the removed resist as a mask. A method for manufacturing a semiconductor device, characterized by comprising the step of cutting out the source and drain regions shallower than the source and drain regions already formed by humans.