JPS593678A - Parallel synchronous operation controller - Google Patents

Abstract

PURPOSE:To hold synchronism securely, by dividing the frequency of an input clock signal through plural microcomputers and putting one computer in frequency dividing operation synchronously with the timing of the frequency-divided signal generation of the other specific computer. CONSTITUTION:The clock signal CK of an oscillator 4 is inputted to terminals ia and -ia of the processor 2a of a specific computer 1a to output a frequency- divided signal Cm. When the frequency-divided signals Cm and Cs of processors 2a and 2b are both at ''0'', an ENR6 generates an output with a level ''1''. An FF7 is triggered by a leading edge of the CK and its output goes up to ''1''; and the CK is inputted to the terminals ia and -ia of the processor 2b through an AND8 to start outputting a frequency-divided signal Cs. Inputs to the ENR6 go up and down to ''1'' and ''0'' and its output goes down to ''0'' to cut off the signals to the processor 2b. When the CK goes down to ''0'', the ENR6 generates the output again and the gate 7 also generates the output. Thus, the timing of frequency-divided signal formation is made coincident and the synchronism is held securely.

Description

Detailed Description of the Invention This @1 guy has a parallel synchronous operation in which multiple microcomputers operate in parallel and synchronously by dividing the input clock signal using a built-in frequency dividing circuit and forming a branch signal for controlling operation timing. Regarding the control device, by using a simple circuit, the operation control timing of each computer is made to match, and the operation start time of each computer is made to be the same, and l
The purpose is to improve the reliability of control by transmitting various operation command signals of the A-section device to each computer in synchronization with the frequency-divided signals whose formation timings coincide with each other to the appropriate size.

Conventionally, microcomputers have been integrated into integrated circuits and have been designed to improve functionality and processing speed, or they have lacked full-fledged fault diagnosis functions like those of large computers. When high reliability is required for devices using microcomputers (hereinafter referred to as computers), one important circuit part is configured with a parallel redundant system such as N out of M to detect failures and Processing needs to be done automatically.

In order to configure the aforementioned parallel redundant system and detect failures early and reliably, it is convenient to install multiple computers in parallel, but it is necessary to synchronize the machine cycles of each computer to perform parallel synchronous operation. be.

However, for example, computers such as Intel's 8085 A processor processor have a built-in frequency divider circuit that divides the input clock signal to form a divided signal for operation timing control. When a plurality of computers are used, even if the same clock signal is input to each computer, the timings of forming the frequency-divided signals of each computer do not match, and therefore the operation control timings of each combination sensor do not match.

It becomes impossible to match the machine cycles of each computer, and it becomes impossible to perform parallel synchronous operations. Furthermore, in order to perform parallel synchronous operation, it is necessary to synchronize the start and point in time of each computer's operation.

Furthermore, each computer operates in synchronization with the frequency-divided signal, and various operation command signals such as interrupt commands from external devices are sent to each computer asynchronously with the frequency-divided signal of each computer. When performing parallel synchronous operation, an operation command signal from an external device is sent to each computer in synchronization with the operation timing of each computer.
You need to be able to squeeze it in.

This @river was created with the above points in mind, and the frequency was divided by a frequency divider circuit with a built-in clock signal, which was manually operated, to form a frequency divided signal for the shift F timing control. a plurality of microcomputers, a branch signal control circuit that matches the formation timing of the divided signal of each of the computers based on the formation timing of the divided signal of a predetermined computer; A reset control circuit that simultaneously cuts off the reset of each of the computers after the coincidence occurs and synchronizes the operation start point of each of the computers; The parallel synchronous operation control device is characterized by comprising a command signal control circuit that causes each of the computers to receive the command signal in synchronization with the frequency-divided signal.

Therefore, the division signal control circuit forms the frequency-divided signals of each computer at the same timing, and the operation control timings of the valley computers coincide, and the reset control circuit allows each computer to have the same operation timing. Since the center station is transmitted simultaneously, each computer's operation f' [start time is the same, and furthermore, the command signal control circuit is used to synchronize the operation command signal of the external device with the branch signal, and each computer's KKy is transmitted at the same timing. , is sent out asynchronously to the frequency-divided signal f
It is possible to have the operation command number 1g of the external device that has been sent to each computer at the same timing synchronized with the branch signal, and it is possible to synchronize the machine cycles of each computer, allowing accurate parallel synchronous operation. It is possible to improve the reliability of control.

At the same time, the parallel synchronous operation control device d of the present invention will be explained with reference to the drawings starting from FIG. 1 showing an embodiment thereof.

In the %1 diagram, (1a) and (tb) are the first @2 computers consisting of microcomputers, which are Intel's 8085 A type processor (2a), which has a built-in frequency dividing circuit for the input clock number 1g. , (21) and peripheral circuits (8a) and (8b), respectively, and clock input terminals (ia) for both processors (2a) and (2b), respectively.

An inverted clock input terminal (ia), a reset input terminal (ib), first to third command input terminals (ic), (
'id), (ie) and a branch output terminal (oa), and the inner peripheral circuits (3a), (3b) are provided with first to third command input terminals (if), (ig), respectively.
, (ih), L'tx, Vr, and third command output terminals (ot+), (oc), and (od) are provided.

When the 8085 A-type Prosensor inputs a clock signal to the clock input terminal and inputs an inverted clock signal to the inverted clock input terminal, the built-in frequency dividing circuit operates to divide the clock signal into two. A frequency-divided signal of the frequency-divided waveform is output from the division output terminal, and the processor operates in synchronization with the frequency-divided signal, for example, a logic 0 (hereinafter referred to as "II O") for a reset command.
When the reset signal (hereinafter referred to as ++ 1 ++) is input to the reset input terminal, the logic of the divided signal after inputting the reset signal A reset signal is input in synchronization with this change, and the processor is initially reset, and in synchronization with a change in which the branch signal or II O++ rises again, the reset output terminal of the processor ( (not shown) to °I'' glue cent indication signal.

That is, a signal indicating that the device is in a reset state is output.

Furthermore, when the reset signal is input and the level of the reset output terminal rises from 0" to "I", the first falling of the divided signal from 11111 to 'O" after the reset signal is cut off. In synchronization with the change, it is detected whether the reset signal is cut off, and in synchronization with the change in which the frequency divided signal rises again from II O'' to °I'', l from the reset output terminal is detected.
! The reset display signal 11' is cut off and the processor starts operating according to the program.

In addition, in FIG. 1, (4) a Cronk oscillator that outputs the rl'i Cronk signal to the clock input terminal (ia) of the processor (2a), and (5) a clock oscillator that inverts the clock signal and outputs the clock signal to the clock input terminal (ia) of the processor (2a). a first inverter that outputs an inverted clock signal to its input terminal (ia); (6) an exclusive NOR gate (hereinafter referred to as ENR) to which frequency-divided signals from both processors (la) and (lb) are input;
.

(7) This is the 17th ring flop to which the output signal of NkL C51 is input to the data input terminal (d), and the clock signal is input to the trigger input terminal (tr). (
8) is the first one where a clock signal is input to the input terminal of
The output signal of the Q output terminal ((1) of the flip-flop t'/) is input to the input terminal of the flip-flop t'/), and the output signal is output to the clock input terminal (ia) of the processor (2b). (9) is EN Fan (6),
A divided signal i'l? consisting of a flip 70 amplifier (7) and an AND gate (8). l control circuit, (1 is 7 limp 7
This is a second inverter that inverts the output signal of the Q output terminal (ql) of the amplifier (7) and outputs it to the inverted clock input terminal (ia) of the processor (2b).

Furthermore, (1)) is the lth NOR gate whose input terminal is connected to the frequency division output terminal (oa) of both processors (2a) and (2b), and (121 is the NOR gate (121) is the output signal of the NOR gate (11J) or the trigger input terminal ( tr), and the J:l input terminal (q) is connected to the cent input terminal (i) of both processors (ta) and (tb), respectively.
b) connected to.

+l: m U NOR gate (11) and flip-flop (reset m1 circuit consisting of 121, +141 is reset having Schmitt circuit (15)) 1ll (with -
The output terminal of the Schmitt circuit (15j) is connected to the data input terminal (d) of the flip-flop (121) and the clear terminal (CI), and the input terminal of the Schmitt circuit (15) is grounded through the cents inch (161k) and 2 It is connected to the power supply terminal (Vc) through the resistor (1η). A capacitor (181 is provided in parallel with the switch (16j), and the resistor (1η) and the capacitor (1
8) forms the time constant circuit when the power is turned on. In both cases, a diode (1!1) is provided in parallel with the resistor (1η).

Then, when the power is turned on, the Cronk oscillator (4) operates, and as shown in Fig. 2 (a), 1 o'clock, C2 o'clock, ts o'clock, 1+ o'clock, C5 o'clock...10'' to 1111 o'clock, respectively.
A clock signal with a period of 1 a that changes to 1 is output from a clock oscillator), and the clock signal is input to a clock input terminal (ia) of a processor (2FL) provided in a predetermined computer, that is, a computer (1B). At the same time, the clock signal is inverted by the inverter (5), and the inverted clock signal is input from the inverter (5) to the inverted clock input terminal (ia) of the processor (2a), and the inverted clock signal is input to the divided output terminal (ia) of the processor (2a). From Oa),
As shown in the same figure (b), when C2 o'clock, 94 o'clock, .

At 65 o'clock, a branch signal with a period Tb that inverts from l'' to '0'' is output.

- At the time of power, Li, and C2, the logic level of the branch signal of the processor (2a) is "0", and also, as shown in FIG.
As shown in FIG.
Since the logic level of the frequency division signal output from a) is also 0', xNft(6) is input with both frequency division signals of 0'', and the logic levels of both frequency division signals match. Because
The output signal of ENH field becomes II l".

And C1 o'clock, C2 o'clock, ts o'clock, 94 o'clock, ts o'clock...
・It O” to tl of the clock signal in each
7 limp flop (7) is triggered by the rising edge of “1”, and the ENR transmitted to the data input terminal (d) is triggered.
Since the output signal of (6) is held at 7 limp 70 limp (7), at +1 and +2 times, it is connected from the Q output terminal (q) of 7 limp 70 limp (7) to AND gate (8) K ” l
” output No. 1B is output.

Therefore, as shown in FIG. 2(d), when a two-period clock signal is input to the clock input terminal (ja) K of the processor (2b) via the AND gate (8), the AND gate (8) The clock signal via the inverter (1
1J, and from the inverter ql to the pro sensor (21
An inverted clock signal obtained by inverting the 2 clock signal is input to the inverted clock input terminal (1a) of the processor (2+)), and a branch signal is about to be output from the branch output terminal (Oa) of the processor (2+)).

However, since the timing of forming the frequency-divided signal of the processor (2a) and the timing of forming the frequency-divided signal of the processor (2b) are different, at +8 o'clock, the processor When the logic level of the branch signal of (2a) becomes 't', the processor (21)
') becomes '0'', and El'J
The output signal of Ij +61 becomes '0''.

Therefore, at 1.3 o'clock, the output signal of the Q output terminal (q) of the 7 limp flop (7) becomes It 011, and as shown in Figure 2 (d), the clock signal from t a 1+@ to 14 o'clock is During the I period, the clock signal from the AND gate (3) to the processor (2+) is analyzed;
The frequency-divided signal of the processor (21) is held at '0'.

Then, as shown in FIG. 2 (IJ), at Ca1, the frequency division signal of the processor (2a) becomes 0'', and the processor (
Since the logic level of the division signal of 2a) and the logic level of the frequency division signal of the processor (2b) match,
As shown in the figure, the AND gate (8) is connected to the PROSENSOR (2).
+))), and at this time, the formation timing of the branch signal of the processor (2a) and the formation timing of the branch signal of the processor (2b) coincide in synchronization with the clock signal. As shown in (b) and (c), after 1 and 41 gin, both branch signals change in the same phase.

First, when the power is turned on, the input of the Schmitt circuit (15) becomes '0'', so the resistor f171 and the capacitor (1
81 and Schmitt circuit (predetermined time determined by 15j,
・Diagram 2 (+3) As shown in K, Schmint circuit (''
The output signal of 5j is held at 41011, and the output signal of Schmitt cycle @ (151 is “0”, so the flimp-fromp (121 is cleared and the Q of 121 is The output signal of output terminal (q) is held at 0''.

Both pro sensors (la), (lb) glue cent input terminal (
The IT OIJ signal is input to ib). Note that the above-mentioned predetermined time is until the phases of both branch signals match.

The time is set to be sufficiently longer than the time of .

After a predetermined period of time has elapsed, as shown in FIG. 2(e),
At f and x after time t5, the output signal of the unit mint circuit 115) changes from '0''2 to 't'VC'z, and 7 IJ
77'' 7o-amp (721 reset is divided by m, same figure (+)), (C) As shown in each, the first '1' of the same signal at 7 o'clock after tx o'clock. Due to the change from `` to 110 +7, the output signal of NOR gate +111 changes from IJ 011 to ``l'', 7 limp 70 ring (121 is triggered, and at this time, the data input terminal (d ), the output signal of the Schmint circuit M (151 I'' is input, so the output of the Q output terminal (q) of the 7 rip 70 amplifier (12) at tz is No. 1 becomes "K", the reset signals of both processors (2a) and (2b) are cut off at the same time, and both processors (2a) and (2b) At the time tz after the center signal is cut off, both branch signals change from "0" to 111" at the same time, and the reset signal is cut off in synchronization with the change of both branch signals from °°0" to l". is detected, and both microprocessors (2a).

(2b) simultaneously starts executing the input program from the beginning.

Furthermore, when the reset switch (16) is operated,
Due to the operations described above and 11, both processors (2a), (
21]) The Nocent signal is simultaneously interrupted, and both processors (2a) and (213) start executing the program from the beginning at the same time.

That is, by the frequency division signal control circuit (9), based on the timing of formation of the frequency division signal by the frequency division circuit of the computer (1a), the divisible signals of both computers (Ia) and (Ib) are simultaneously set to 0. ,■” Input the computer (Ib) K clock signal only when
The formation timing of the frequency-divided signal in (1b) is determined by the computer (
Coincide with the formation timing of the divided signal of La).

The operation control timings of both computers (la) and (Ib) are made to match.

The reset control circuit (131) controls both computers (Ia) at power-on and reset operation.

After the formation timing of frequency division number 1g of (117) coincides.

At the timing when the branch signals of both computers (la) and (lb) change from l'' to "0" at the same time, the reset signal to both computers (1a) and (lf)) is cut off, and both computers (Ia) and tb) at the same timing synchronized with the branch signal, and both computers (
la).

(lb) to coincide with the start point of operation.

Furthermore, in FIG. 1, it is an external device having 1/'i first to third command output terminals (Oe of), (Og), and from the command output terminal (Oe) to the inner peripheral device (3a).
, (3b), the interrupt command signal of IT1'' is outputted to the command input terminal (3b), and the inner peripheral device (3a,) is output from the command output terminal (Of).

The hold command signal of the command input terminal (ig) K"'" of (3b) is output, and the command input terminal (ih) of the inner peripheral device m (3i1) and (3b) is output from the command output terminal (og).
[Lay 1 +1 ready command signal is output. (21
), the input terminal is both 1@edge so f! (8a) and (3b) are connected to the command output terminals (()1 and are the second AND gates, and interrupt command signals are simultaneously input from the inner peripheral devices (8a) and (31)1, respectively. When the input terminal is input to peripheral device #' (3a), (3!Q's command n) power terminal (OG
>K is the third AND gate connected to the terminal, and hold command signals are simultaneously input from each of the inner peripheral devices (3a), (31)), and the output signal is 'l'.
” K. (z3) has input terminals on both peripherals, g (3
It is an rg 4 AND gate connected to the command output terminal (ad,) of a) and (3b), and is an inner peripheral device (3FL).

(8b) When letty signals are input from each at the same time, the output signal becomes 'I'K.

Also, (24+ and +251) have input terminals for both processors (2B).

(2b) connected to the divided output terminal (oa) of the second gate) and the fifth ant' gate, both processors
Only when the divided signals of a) and (2b) become '0'K at the same time, the output signal of the NOR gate (to) becomes 'l', and the divided signals of both processors (2B) and (2b) become 'K' at the same time. 'l
” only when the output signal of the AND gate is °l
(261 is the 87th ring 70 amplifier connected to the output terminal of 2#, the trigger input terminal (tr) is a NOR gate, and the data input terminal (d) is an ant gate) +2
It is connected to the Q output terminal (q
) are both processors (2B), (21υ command input terminal (
ic). @ is the trigger input terminal (Lr)
is the 47th lip 70 tube connected to the output terminal of the NOR gate (Yen), the data input terminal (d) is connected to the attraction terminal of the AND gate (company), and the Q output terminal (
q) is connected to the command input terminal (1d) of both processors (2a) and (2b) J'V.

I'm here. G) is the 57th ring flop whose trigger input terminal (1) is connected to the output terminal of AND gate G31, and whose data input terminal (d) is connected to the output terminal of AND gate G31, and whose Q output terminal is connected to the output terminal of AND gate G31. (q) is connected to the command input terminal <re)K of both processors (28) and (2b).

And the command output terminal (o) of the unit device (20)
When an interrupt command signal is output from c), the command signal is input to the computer 121+ via the inner peripheral circuits (3a) and (8b), respectively.2 At this time, the inner peripheral circuit (3a).

Only while the interrupt command signal via (8b) is simultaneously input, the output signal of the anime game-1-+f51 becomes I", and similarly, the command output terminal (or) of the external device (20),
Even if the hold command signal and 1/Teiichi command gogo are output from each (og), the inner peripheral circuit (3
a).

Only while the hold command signal via (30) is input at the same time, the output signal of Antogame 1122+ becomes l",
The attractive force 1 of the AND gate 11 is applied only while the ready command signals via the inner peripheral circuits (3a) and (8b) are simultaneously input.
No. 6 becomes °゛l'', and both computers (la) and (l
The deviation in the output timing of each command signal from each of the inner peripheral circuits (8a) and (31)), which is caused by the error in the signal transmission time in b), is corrected.

Furthermore, only when the branch signals of both processors (2a) and (2b) become "P0" at the same time, the output signal of the NOR gate 241 becomes "'1" and the flimp 70+2
6+.

θ or NOAD) from '0'' of f241 output signal
Since it is triggered by the beginning of the "work", both processors (2a) and (2b) receive the branch signal or the simultaneous K ``I''.
The interrupt command signal and the hold command signal are transmitted to the respective data input terminals (d) of J and Clh, respectively. rut, (2η each KN and 7 limps 70 amps + 261.1.//l each il, from both processors (2FL).

(An interrupt command signal and a hold command signal are output at 21, respectively, to both processors (2a) and '(2b),
Is it the divided signal of the image processors (2a) and (2b)...?
Interrupt command 'IFT' is issued at the same timing when changing from . to 0.

Each hold command signal is sent out.

In addition, when the field IFj of the 11th pro sensor (2a) (and gate value only when the 21st branch signals become ``I'' at the same time) becomes ``I'', the flimp 70 tube becomes ``AND''. 0″ to 11 of the output signal of the gate □□□)
Since it is triggered at the rising edge of 1”, both pro sensors (
2a) and (2b) The frequency-divided signals are simultaneously K ``0''
When the voltage changes from 7 to 7, the data input terminal (d) of the 7-lip 70 knob (28) is transmitted and the ready command signal is sent to the 7-lip 70 amplifier (28). A ready signal is output from the flimp 70 amplifier (28) to both processors (2a), (2b), and both processors (2a), (21, both processors (2a),
A ready command signal is sent to branch station 1 of (21J) at the same timing when the number changes from 11011 to 'I'.

In other words, in the 5os5A type processor, the frequency divided signal is
l II's! : Interrupt command signal and hold command signal are incorporated into key, and the branch signal is 110 II to '■
(24+ and AND gate value), both processors (2a), (2b)
The timing of forming the frequency-divided signals of both processors (
When the branch signals 2a) and (2b) change from I'' to '0'' at the same time, the 7-rip 70-amp t261. (Trigger (5), and when the divided signals of both processors (2a) and (2b) change from "0" to "It1" at the same time, trigger the 7-lip flop (28), and after the formation timings match, Both processors (2a), (
21, the interrupt command signal, hold command IJ, and ready command signal 'rL are sent to both computers (
la), (Ib) Interrupt at v1-1 timing,
Enjoy the hold and ready operation command signals.

Therefore, the five-car computer (la
), (,lb) The formation timing of the frequency division signal for the operation timing system @1 of it is based on the frequency division 1δ number system @j circuit t.
9Jeζ, both computers (la), (Ib
)'s internal movement f' timing is controlled identically, and both computers (la) and (Ilr) are reset simultaneously by the reset control circuit t131. The operation start points coincide.Furthermore, the Vζ command signal control circuit (29) converts the interrupt command signal, hold command signal, and ready command signal output from the external device 12U) into the post-trap branch signal whose formation timing coincides. It is possible to import data into both computers (RA) and (LB) at the same synchronized timing.

It is possible to match the machine cycles of computers (la) and (Ib) with a simple circuit.
).

(lb) can be operated accurately in parallel and synchronously, for example, by configuring a parallel redundant system with both computers (Ia) and (II), it is possible to quickly and accurately detect faults and perform fault processing. can.

The AND gate t211~(23j was set up).

Due to the difference in signal transmission time between both computers (la) and (II), both peripheral devices it (3a) and (3b)
) The timing deviation of each command signal from each is corrected.

It should be noted that although the present invention can be applied to a computer having a microprocessor other than the 8085 type A microprocessor of the above embodiment, it is of course applicable to a computer having no peripheral device.

In addition, when the number of computers increases, the number of branch/number control circuits (9) is increased, the reset control circuit (13I NOR gate + 111 is formed with a multi-input NOR gate, and the command signal control circuit 129+
It is sufficient to form a NOR gate (for example, an AND gate (25j is a multi-input type) r gate, and an AND gate, respectively).

[Brief explanation of drawings]

The drawings show an embodiment of the parallel synchronous operation 1d1] control device of the present invention, FIG. 1 is a block wiring diagram of the mounting section, and FIG.
) to (r) are timing charts for explaining the operation of FIG. (la), (lb)...Microcomputer, (4
)... Clock generator, (9)... Frequency division signal control circuit, [31... Reset control circuit, Rigid... External device, C9)... Command signal control circuit. Agent: Patent Attorney Ryutabe Fujita

Claims (1)

[Claims] ■ A plurality of microcomputers which divide the input clock signal by a built-in frequency divider circuit to form a frequency division signal for operation timing control, and a plurality of microcomputers that divide the input clock signal by a built-in frequency divider circuit, and based on the formation timing of the frequency division signal of a predetermined computer. a branch signal control circuit that synchronizes the formation timing of the frequency-divided signals of each of the computers; and a branch signal control circuit that simultaneously cuts off the reset of each of the computers after the formation timing of the frequency-divided signals coincides with each other, and determines the start point of operation of each of the computers. and a command signal control circuit that causes the operation command signals of the external device EL to be stored in each of the computers in synchronization with the frequency-divided signal after the formation timings match. A parallel synchronous operation control device characterized by: