JPS6010626A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6010626A
JPS6010626A JP58119611A JP11961183A JPS6010626A JP S6010626 A JPS6010626 A JP S6010626A JP 58119611 A JP58119611 A JP 58119611A JP 11961183 A JP11961183 A JP 11961183A JP S6010626 A JPS6010626 A JP S6010626A
Authority
JP
Japan
Prior art keywords
etching
amount
measuring
hole
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58119611A
Other languages
Japanese (ja)
Inventor
「たか」橋 広成
Hiroshige Takahashi
Hirokazu Miyoshi
三好 寛和
Akira Nishimoto
西本 章
Akira Ando
亮 安藤
Moriyoshi Nakajima
盛義 中島
Yoko Matsuno
松野 葉子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58119611A priority Critical patent/JPS6010626A/en
Publication of JPS6010626A publication Critical patent/JPS6010626A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To accurately etch by simultaneously forming a monitoring pattern for measuring the etching amount larger than a contacting hole at the place except the place where a semiconductor element is formed at the time of forming the hole. CONSTITUTION:An interlayer insulating film 2 is formed on a silicon substrate 1, and patterned. An n<+> type diffused layer 3 is formed on the substrate 1. A monitoring pattern 4 for measuring the etching amount of 5mumX5mum is formed on the place except a semiconductor element. The pattern 4 is formed simultaneously with the formation of a contacting hole. Since the etching amount is monitored by the pattern 4, the hole can be extremely accurately etched.

Description

【発明の詳細な説明】 この発明は、微細なパターンの形成時において、正確な
エツチング量の測定ができるようにした半導体装置の製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that allows accurate measurement of the amount of etching when forming fine patterns.

まス、従来のエツチング量のフントロールについて説明
する。
First, the conventional etching amount control will be explained.

従来、フンタクトホールの形成は、ドライエツチング装
置により行い、エツチング量は装置如何いている分光分
析器により検知さjている。この分光分析器により検知
された信号によりコンタクトホールが形成された場合に
、ドライエツチング装置は余分なエツチングを行わない
ためにエツチングを停止する。一般にこの方法は、エツ
チング種のシグナル強度の変化量として検出されるもの
である。このため゛に、微細パターン次形成しフンタク
トホールの大きさを小さくしていった場合、エツチング
種によるシグナルの変化量が少なくなり、正確なエツチ
ング量な測定することが困難になるという欠点があった
Conventionally, dry etching equipment has been used to form dry etching holes, and the amount of etching has been detected using a spectroscopic analyzer in the equipment. When a contact hole is formed based on the signal detected by the spectroscopic analyzer, the dry etching device stops etching to prevent unnecessary etching. Generally, this method detects the amount of change in signal intensity of the etching species. For this reason, when a fine pattern is formed and the size of the hole is made smaller, the amount of change in the signal due to the etching species decreases, making it difficult to accurately measure the amount of etching. there were.

この発明は、上記のような従来のものの欠点を除去する
ためKなされたもので、微細なコンタクトホールの形成
において、エツチング量の測定txコンタクトホールと
同様の層間絶縁膜な持ち、大きさがコンタクトホールよ
りも大きなエツチング量測定用のモニタパターンを半導
体素子以外の場所にコンタクトホールの形成と同時に形
成し、このモニタパターンを監視することにより、正確
にエツチングされた微細なコンタクトホールを持った半
導体装置な製造することを目的としている。
This invention was developed in order to eliminate the drawbacks of the conventional ones as described above, and is used to measure the amount of etching in the formation of fine contact holes. By forming a monitor pattern for measuring the amount of etching, which is larger than the hole, at the same time as forming the contact hole in a location other than the semiconductor element, and monitoring this monitor pattern, a semiconductor device with precisely etched fine contact holes can be created. The purpose is to manufacture

以下この発明の一実施例を図面について説明する。An embodiment of the present invention will be described below with reference to the drawings.

なお、この実施例では、128KFAMO8のコンタク
トホールのエツチングについて述べることにする。
In this example, etching of a contact hole of 128K FAMO8 will be described.

図面において、1はシリコン基板、2は前記シリコン基
板1上に生成さj1パターンニングさ4た層間絶縁膜、
3は前記シリコン基板1に形成さ4たnl 拡散層、4
は半導体素子以外のところに形成された大きさが、例え
ば5μm X 5μm のエツチング量測定用のモニタ
パターンである。
In the drawings, 1 is a silicon substrate, 2 is an interlayer insulating film that has been patterned on the silicon substrate 1,
3 is a diffusion layer 4 formed on the silicon substrate 1;
is a monitor pattern for measuring the amount of etching formed outside the semiconductor element and having a size of, for example, 5 μm×5 μm.

次に動作について説明する。Next, the operation will be explained.

コンタクトホール(図示せず)は、厚さ8000久の層
間絶縁膜2に2μmX2μmの大きさのものヲ形成する
ものとする。この時、コンタクトホールとなる部分it
よびそのエツチング量の測定1行うためにコンタクトボ
ールとは別の場所に形成さね、た58mX5μm の大
きさのモニタパターン4以外の部分は、レジストによっ
て覆われている。
A contact hole (not shown) having a size of 2 μm×2 μm is formed in the interlayer insulating film 2 having a thickness of 8,000 mm. At this time, the part that will become the contact hole
In order to carry out measurement 1 of the amount of etching, the portions other than the monitor pattern 4, which was formed at a location separate from the contact ball and had a size of 58 m x 5 μm, were covered with resist.

エツチングはドライエツチング装置によって行わ4、エ
ツチング量はエツチング量測定用のモニタパターン4に
おける分光分析器によって検出している。コンタクトホ
ールとなる部分およびエツチング量測定用σ)モニタパ
ターン4の層間絶縁膜2の厚さは互いに8000Aであ
るので、エツチング量測定用のモニタパターン4により
完全にエツチングさ4たという信号がドライエツチング
装置に伝わること匠よりエツチングは停止する。この方
法によって行ったコンタクトホールを顕微鏡観察および
SEM観察を行ったところ、2μmX2μmの大キさの
コンタクトホールは完全にエツチング’g it ”c
 57ts・ 1 なお、上記実施例では、128に’FAMO8の製造に
ついて述べたが、微細なコンタクトホールをドライエツ
チング装置によって正確なエツチングを行う必要のある
半導体装置であるならば、一般的な半導体装置について
も有効であることはいうまでもない。
Etching is performed by a dry etching device 4, and the amount of etching is detected by a spectroscopic analyzer in a monitor pattern 4 for measuring the amount of etching. Since the thickness of the interlayer insulating film 2 of the portion that will become the contact hole and the monitor pattern 4 for measuring the amount of etching (σ) is 8000A, the monitor pattern 4 for measuring the amount of etching sends a signal indicating that the etching has been completely etched. Etching stops when the information is transmitted to the device. Microscopic and SEM observations of contact holes made using this method revealed that contact holes with a size of 2 μm x 2 μm were completely etched.
57ts・1 In the above embodiment, the manufacturing of FAMO8 was described in 128, but if the semiconductor device requires precise etching of fine contact holes using a dry etching device, it can be etched using a general semiconductor device. Needless to say, it is also effective.

以上説明したように、この発明は、半導体装置の製造に
際し、微細なコンタクトホールl半導体素子が形成され
ている以外の場所に前記微細なコンタクトホールよりも
大きいエツチング量測定用のモニタパターンな同時比形
成し、このモニタパターンを用いてエツチング量のモニ
タケ行うようにしたので、微細なコンタクトホールのエ
ツチングを極めて正確に行うことができ、そのため安定
した半導体装置が得られる利点がある。
As explained above, the present invention provides a simultaneous ratio of a monitor pattern for measuring the amount of etching that is larger than the fine contact hole in a location other than the fine contact hole where the semiconductor element is formed when manufacturing a semiconductor device. Since the etching amount is monitored using this monitor pattern, it is possible to etch fine contact holes extremely accurately, which has the advantage that a stable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

図面はこの発明の一実施例を説明するための半導体装置
の要部の断面図である。 図中、1はシリコン基板、2は層間絶縁膜、3はn十拡
散層、4はエツチング量測定用のモニタパターンである
。 代理人 大岩 増雄 (外2名) 2
The drawing is a sectional view of a main part of a semiconductor device for explaining an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is an interlayer insulating film, 3 is an n+ diffusion layer, and 4 is a monitor pattern for measuring the amount of etching. Agent Masuo Oiwa (2 others) 2

Claims (2)

【特許請求の範囲】[Claims] (1)半導体素子間の配線な行う場合に形成するコンタ
クトホールσ〕エツチングにおいて、前記コンタクトホ
ール形成時に、層間絶縁膜のエツチング量をコントロー
ルするために前記コンタクトボールより大きい所定の大
きさl有するエツチング量測定用のモニタパターンを前
記半導体素子以外の場所に前記コンタクトホールと同時
に形成し、このモニタパターンの形成完了l検出して前
記エツチングを完了させることを特徴とする半導体装置
の製造方法。
(1) Contact hole σ formed when wiring between semiconductor elements] In etching, an etching having a predetermined size l larger than the contact ball is used to control the amount of etching of the interlayer insulating film when forming the contact hole. A method for manufacturing a semiconductor device, characterized in that a monitor pattern for measuring the amount of etching is formed at a location other than the semiconductor element at the same time as the contact hole, and completion of the formation of the monitor pattern is detected to complete the etching.
(2) エツチング量測定用のモニタパターンの大きさ
は、−辺が5μm以上の四角形であることを特徴とする
特許請求の範囲第(1)項記載の半導体装1行の製造方
法。
(2) The method for manufacturing one row of semiconductor devices according to claim (1), wherein the size of the monitor pattern for measuring the amount of etching is a rectangle with a negative side of 5 μm or more.
JP58119611A 1983-06-29 1983-06-29 Manufacture of semiconductor device Pending JPS6010626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58119611A JPS6010626A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119611A JPS6010626A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6010626A true JPS6010626A (en) 1985-01-19

Family

ID=14765698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58119611A Pending JPS6010626A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6010626A (en)

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