JPS60140586A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS60140586A JPS60140586A JP58247008A JP24700883A JPS60140586A JP S60140586 A JPS60140586 A JP S60140586A JP 58247008 A JP58247008 A JP 58247008A JP 24700883 A JP24700883 A JP 24700883A JP S60140586 A JPS60140586 A JP S60140586A
- Authority
- JP
- Japan
- Prior art keywords
- speed
- power consumption
- memory circuit
- control terminal
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 19
- 239000013256 coordination polymer Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、メモリ回路、特に動作速度及び消費電力が可
変である集積化されたメモリ回路に関する。TECHNICAL FIELD The present invention relates to memory circuits, and particularly to integrated memory circuits with variable operating speed and power consumption.
（従来技術）
集積回路化されたメモリ（以下、ＩＣメモリという。）
は近年性能が改善され、動作速度については高速化の一
途’１ｉｌ−７’Ｃどっているが、その応用面から見た
場合、必ずしも高速動作だけが必要とされる性能ではな
く、むしろ速度よりも消費電力が少いことが必要である
場合も多い。すなわち、ＩＣメモリヲ応用するシステム
の性格に応じて適当な動作速度と消費心力が選ばれる。(Prior art) Integrated circuit memory (hereinafter referred to as IC memory)
Performance has been improved in recent years, and the operating speed continues to increase to '1il-7'C, but from the perspective of its application, high-speed operation is not necessarily the only performance required; rather, it is more important than speed. In many cases, low power consumption is also required. That is, an appropriate operating speed and energy consumption are selected depending on the characteristics of the system to which the IC memory is applied.
一方、ＩＣメモリは技術の進歩に伴い、その速度・電力
積は小さくなって向上していく傾向にあるが、第１図に
示すように、同一技術レベルのものであれば、その速度
・電力積はほぼ一定になるという基本的な法則が一般的
に認められる。On the other hand, with the advancement of technology, the speed and power product of IC memory tends to decrease and improve. A basic law is generally accepted that the product is approximately constant.
さて、ＩＣメモリの製造業者は、上記したような応用面
からの要求を満たすべく、同一技術レベルであって速度
及び心力の異なるＩＣメモリを複数品種設計製造して来
た。Now, in order to meet the above-mentioned application requirements, IC memory manufacturers have designed and manufactured multiple types of IC memories of the same technology level but with different speeds and forces.
しかし、この場合、製造規模の拡大によるコストダウン
、いわゆる量産効果が出にくいという欠点があった。あ
るいは、多くのユーザーの要求をすべて満たすにはあま
りに多くの品種を取揃える必要がちるという欠点があっ
た。However, in this case, there was a drawback that it was difficult to achieve cost reductions due to expansion of the manufacturing scale, so-called mass production effects. Another drawback is that it is often necessary to offer too many varieties to satisfy all the demands of many users.
（発明の目的）
本発明の目的は、上記欠点を取除き、動作速度と消費電
力については、ユーザー側で自由に可変可能なメモリ回
路を提供することにある。(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a memory circuit whose operating speed and power consumption can be freely changed by the user.
（発明の構成）
本発明のメモリ回路は、少くとも一つの制御端子と、該
制御端子に印加される制御信号レベルに応じて動作速度
及び消費心力を可変とする速度・電力制御手段とを含む
ことから構成される。(Structure of the Invention) The memory circuit of the present invention includes at least one control terminal, and speed/power control means for varying the operating speed and power consumption according to the control signal level applied to the control terminal. It consists of things.
（実施例）
以下１本発明の実施例について図面ｔ−参照して説明す
る。(Embodiment) An embodiment of the present invention will be described below with reference to drawing t.
第２図は本発明の第１の実施例の要部を示す回路図でち
る。FIG. 2 is a circuit diagram showing essential parts of the first embodiment of the present invention.
本実施例は、一つの制御端子ｌと、この制御端子ｌに印
加される制御信号ＣＰのレベルに応じて動作速度及び消
費電力を可変とする速度・電力制御手段２とを含むこと
から構成される。This embodiment includes one control terminal l and a speed/power control means 2 that varies the operating speed and power consumption according to the level of the control signal CP applied to the control terminal l. Ru.
速度・′１力制御手段２は、ドレインが電源Ｖｃｃに、
ゲートが制御端子１に共通接続され、ソースがそれぞれ
メモリ回路を構成する回路ブロックＣＢ１．ＣＢｚ、・
・・、ＣＢＮに接続されたディプレッション型ＭＯ８）
ランジスタＱｔ＋ Ｑ”ｅ・・・＋ ＱＮからなってい
る。ここで回路ブロックＣＤＩ、、ＣＢ２． 。The speed/'1 force control means 2 has a drain connected to the power supply Vcc,
Circuit blocks CB1 . CBz,・
..., depression type MO8 connected to CBN)
It consists of transistors Qt+Q"e...+QN.Here, circuit blocks CDI, CB2.
・・・、ＣＢＮは、具体的には例えば、アドレスバッフ
ァ、デコーダ等を表わす。..., CBN specifically represents, for example, an address buffer, a decoder, etc.
本実施例によると、各回路ブロックＣＢ１．ＣＢｚ・・
・、ＣＢＮへの電力供給は、電源Ｖｃｃからそれぞれ各
ＬＶＩＯ８）ランジスタＱｌ、 Ｑ２・・・＊ＱＮ’ｅ
通して行われる。According to this embodiment, each circuit block CB1. CBz...
・Power is supplied to the CBN from the power supply Vcc to each LVIO8) transistor Ql, Q2...*QN'e
It is done through.
従って、制御信号ＣＰの信号レベルに応じてトランジス
タＱｔ、 Ｑ２＊・・・ＱＮのオン抵抗が変化し、制御
信号ＣＰの信号レベルが高くなると、オン抵抗は下がり
、第３図の特性図に示すように、消費心力が増加して動
作速度は速くなる。Therefore, the on-resistance of the transistors Qt, Q2*...QN changes according to the signal level of the control signal CP, and as the signal level of the control signal CP increases, the on-resistance decreases, as shown in the characteristic diagram of Fig. 3. As a result, the amount of mental energy consumed increases and the operating speed becomes faster.
第４図は本発明の第２の実施例の要部を示すブロック図
である。FIG. 4 is a block diagram showing the main parts of a second embodiment of the present invention.
本実施例は、二つの制御端子１’、１“と、この制御端
子１′、ｌ“に印加される制御信号ＣＰ １゜ＣＦ２の
レベルに応じて動作速度及び消費電力を可変とする速度
・電力制御手段２′とを含むことから構成される。This embodiment is a speed converter whose operating speed and power consumption are made variable according to the levels of two control terminals 1', 1'' and control signals CP1°CF2 applied to these control terminals 1', 1''. and a power control means 2'.
速度・′成力制御手段２′は、電源Ｖｃｃと各回路ブロ
ックＣＢＩ、ＣＢ２．・・・、ＣＢＮ間にそれぞれ波列
接続された各３個のディプレッション型ＭＯＳトランジ
スタ（Ｑｌｌ、Ｑｔ２．Ｑｔ３ ）、（Ｑ２１゜Ｑ２２
．Ｑ２３）、°°、（ＱＮｌ、ＱＮ２．ＱＮ３）からな
る回路からなり、ＭＯＳトランジスタＱ”ｍＱ２１．・
・・ＩＱＮＩのゲートはバッファＢ１ｕ介して制御端子
１′に、ＭＯＳ）ランジスタＱ１２１Ｑ２２．・・・１
ＱＮ２のゲートは接地電位に、ＭＯＳトランジスタＱ１
Ｂ、Ｑ２１１．−・・、ＱＮ３のゲートはバッファＢ２
ｔｌ−介して制御卸端子１“にそれぞれ接続されること
からなっている。The speed/force control means 2' is connected to a power supply Vcc and each circuit block CBI, CB2 . ..., three depletion type MOS transistors (Qll, Qt2.Qt3) each connected in wave train between CBN, (Q21゜Q22
．． It consists of a circuit consisting of Q23), °°, (QNl, QN2.QN3), and a MOS transistor Q"mQ21.
...The gate of IQNI is connected to the control terminal 1' via the buffer B1u, and to the MOS) transistor Q121Q22. ...1
The gate of QN2 is connected to the ground potential, and the gate of MOS transistor Q1
B, Q211. --..., the gate of QN3 is buffer B2
tl- to the control terminal 1'', respectively.
すなわち、本実施例におｈては、各回路ブロックＣＢＩ
、ＣＢ２．・・・、ＣＢＮへの電力共給金、各３個のＭ
ＯＳトランジスタ（Ｑｌｌ、 Ｑｔ ２． Ｑｔ ｓ
）。That is, in this embodiment h, each circuit block CBI
, CB2. ..., electricity co-payment to CBN, 3 M each
OS transistor (Qll, Qt 2. Qt s
).
（Ｑ２１． Ｑ２２． Ｑ２ ：ｌ ） 、・−・、（
ＱＮＩ、 ＱＮ２． Ｑ）ｌ ）を通して行うようにし
たものである。(Q21. Q22. Q2 :l) ,...,(
QNI, QN2. Q) l).
従って、制御信号ＣＰＩ、ＣＰ２の論理レベル０．１”
に応じて、動作速度、消費電力が変化する。例えば制御
信号ＣＰＩ、ＣＰ２が共に０”の場合が最も低速かつ低
消費電力となる。Therefore, the logic level of control signals CPI and CP2 is 0.1''
Operating speed and power consumption vary depending on the For example, when the control signals CPI and CP2 are both 0'', the speed is the slowest and the power consumption is lowest.
第ぢ図は、制御信号ＣＰＩ、ＣＰ２の論理レベルに対す
る動作速度、消費電力の特性値示す図で、上記のことが
良く示されている。FIG. 3 is a diagram showing characteristic values of operating speed and power consumption with respect to logic levels of control signals CPI and CP2, and clearly shows the above.
なお、本発明は上記の実施例に限定されることなく１例
えば制＃端子を増やすとか、他の適切な回路を用いても
同様である。It should be noted that the present invention is not limited to the above-described embodiment, and the same effect can be achieved by increasing the number of control terminals, for example, or by using other suitable circuits.
（発明の効果）
以上、詳細に説明したように、本発明によるメモリ回路
は、ｒｌｉｔ制御信号に印加するレペ々によりその動作
速度、消費電力が可変であるので、ユーザー側が必要に
応じてその直ヲ自由に設定できるという効果ヲ有してお
り、実用上の効果は大である。(Effects of the Invention) As described above in detail, the memory circuit according to the present invention has variable operating speed and power consumption depending on the repetitions applied to the rlit control signal, so the user can adjust the operating speed and power consumption as necessary. It has the advantage of being able to be set freely, and has great practical effects.
第１図は動作速度と消費電力の関係を示す特性図、第２
図は本発明の第１の実施例の要部を示す回路図、第３図
はその特性図、第４図は本発明の第２の実施例の要部を
示す回路図、第５図はその特性値を示す図である。
１．１’、１“・・・・・・制御端子、２． ２’・・
・・・・速度・電力制御手段、８１．Ｂ２・・・・・・
バッファ、ＣＢ ｌ、 ＣＢ ２．−・・、 ＣＢＮ・
・・・−回路フｏ ｙ り、ＣＰ。
ＣＰＩ、ＣＰ２・・・・・・制御信号、Ｑｌｌ ＱＫ、
・・； ＱＫ Ｑ”＋Ｑｌ ２１ Ｑｌ ：ｌ、 ＱＫ
１． ＱＫ ２６ ＱＫ ３１・・； ＱＮＩ、拳２
．拳３・・・・・・ディプレッション型ＭＯＳトランジ
スタ
消ｆ−電ガ
峯１回
￥２珂
ｃｐのＬへ１し
早３割
事ダ回Figure 1 is a characteristic diagram showing the relationship between operating speed and power consumption.
The figure is a circuit diagram showing the main part of the first embodiment of the present invention, FIG. 3 is a characteristic diagram thereof, FIG. 4 is a circuit diagram showing the main part of the second embodiment of the invention, and FIG. It is a figure showing the characteristic value. 1.1', 1"...control terminal, 2.2'...
...speed/power control means, 81. B2...
Buffer, CB l, CB 2. --, CBN・
...-Circuit form, CP. CPI, CP2... Control signal, Qll QK,
...; QK Q”+Ql 21 Ql :l, QK
1. QK 26 QK 31...; QNI, fist 2
．． Fist 3...Depression type MOS transistor extinguishing f-Dengamine 1 time ¥2K to L of CP 1 time and 30% as soon as 3 times.
Claims (3)
される制御信号のレベルに応じて動作速度及び消費電力
を可変とする速度・電力制御手段とを含むことを特徴と
するメモリ回路。(1) A memory circuit characterized by comprising at least one control terminal and speed/power control means for varying operating speed and power consumption according to the level of a control signal applied to the control terminal.
が制御端子に共通接続され、ソースがそれぞれメモリ回
路を構成するＮ（Ｎ２２）個の回路ブロックに接続され
たＮ個のディプレッション型ＭＯ８）ランジスタからな
る特許請求の範囲＠（１）項記載のメモリ回路。(2) The speed/power control means consists of N depletion type MO8s whose drains are commonly connected to a power supply, whose gates are commonly connected to a control terminal, and whose sources are connected to N (N22) circuit blocks constituting a memory circuit. A memory circuit according to claim (1) comprising a transistor.
するＮ（Ｎ２２）個の回路ブロック間にそれぞれ接続さ
れた第１．第２．第３のディプレッション型ＭＯ８）ラ
ンジスタの並列接続からなるＮ個の回路からなり、前記
第１のＭＯＳ）ランジスタのゲートは第１のバッファを
介して第１の制ｆ４瑞子に、前記第２のＭＯＳ）ランジ
スタのゲートは接地電位に、前ｉ己第３のＭＯＳ）ラン
ジスタのゲートは第２のバッファを介して第２の制御端
子にそれぞれ接続されてなる特許請求の範囲第（１）項
記載のメモリ回路。(3) The speed/power control means is connected between the N (N22) circuit blocks constituting the power supply and memory circuits, respectively. Second. The third depletion type MO8) consists of N circuits each consisting of a parallel connection of transistors, and the gate of the first MOS transistor is connected to the first transistor f4 through a first buffer, and the gate of the second MOS The gates of the third MOS transistors) are connected to the ground potential, and the gates of the transistors are connected to the second control terminal via the second buffer, respectively. memory circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58247008A JPS60140586A (en) | 1983-12-28 | 1983-12-28 | Memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58247008A JPS60140586A (en) | 1983-12-28 | 1983-12-28 | Memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60140586A true JPS60140586A (en) | 1985-07-25 |
Family
ID=17157009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58247008A Pending JPS60140586A (en) | 1983-12-28 | 1983-12-28 | Memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60140586A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321658A (en) * | 1990-05-31 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Semiconductor memory device being coupled by auxiliary power lines to a main power line |
-
1983
- 1983-12-28 JP JP58247008A patent/JPS60140586A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321658A (en) * | 1990-05-31 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Semiconductor memory device being coupled by auxiliary power lines to a main power line |
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