JPS60180151A - バンプ付基板及びその製作法 - Google Patents

バンプ付基板及びその製作法

Info

Publication number
JPS60180151A
JPS60180151A JP59035280A JP3528084A JPS60180151A JP S60180151 A JPS60180151 A JP S60180151A JP 59035280 A JP59035280 A JP 59035280A JP 3528084 A JP3528084 A JP 3528084A JP S60180151 A JPS60180151 A JP S60180151A
Authority
JP
Japan
Prior art keywords
bumps
bump
substrate
paste
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59035280A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0345900B2 (2
Inventor
Tetsuo Nomura
哲雄 野村
Hiroyuki Shinya
新屋　裕之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Narumi China Corp
Original Assignee
Narumi China Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Narumi China Corp filed Critical Narumi China Corp
Priority to JP59035280A priority Critical patent/JPS60180151A/ja
Publication of JPS60180151A publication Critical patent/JPS60180151A/ja
Publication of JPH0345900B2 publication Critical patent/JPH0345900B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP59035280A 1984-02-28 1984-02-28 バンプ付基板及びその製作法 Granted JPS60180151A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59035280A JPS60180151A (ja) 1984-02-28 1984-02-28 バンプ付基板及びその製作法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59035280A JPS60180151A (ja) 1984-02-28 1984-02-28 バンプ付基板及びその製作法

Publications (2)

Publication Number Publication Date
JPS60180151A true JPS60180151A (ja) 1985-09-13
JPH0345900B2 JPH0345900B2 (2) 1991-07-12

Family

ID=12437367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59035280A Granted JPS60180151A (ja) 1984-02-28 1984-02-28 バンプ付基板及びその製作法

Country Status (1)

Country Link
JP (1) JPS60180151A (2)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235597A (ja) * 1985-08-08 1987-02-16 日本電気株式会社 配線基板
JPS62282490A (ja) * 1986-05-30 1987-12-08 シャープ株式会社 部品の端子接続方法
US6383327B1 (en) * 1986-12-24 2002-05-07 Semiconductor Energy Laboratory Co., Ltd. Conductive pattern producing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235597A (ja) * 1985-08-08 1987-02-16 日本電気株式会社 配線基板
JPS62282490A (ja) * 1986-05-30 1987-12-08 シャープ株式会社 部品の端子接続方法
US6383327B1 (en) * 1986-12-24 2002-05-07 Semiconductor Energy Laboratory Co., Ltd. Conductive pattern producing method
US7288437B2 (en) 1986-12-24 2007-10-30 Semiconductor Energy Laboratory Co., Ltd. Conductive pattern producing method and its applications

Also Published As

Publication number Publication date
JPH0345900B2 (2) 1991-07-12

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