JPS60181055U - 半導体インピーダンス構造 - Google Patents

半導体インピーダンス構造

Info

Publication number
JPS60181055U
JPS60181055U JP1985060174U JP6017485U JPS60181055U JP S60181055 U JPS60181055 U JP S60181055U JP 1985060174 U JP1985060174 U JP 1985060174U JP 6017485 U JP6017485 U JP 6017485U JP S60181055 U JPS60181055 U JP S60181055U
Authority
JP
Japan
Prior art keywords
conductive path
intrinsic
substrate
impedance structure
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985060174U
Other languages
English (en)
Inventor
バーノン　ジヨージ　マツケニイ
ツイウ　チウ　チヤン
Original Assignee
エスジーエス―トムソン　マイクロエレクトロニクス，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エスジーエス―トムソン　マイクロエレクトロニクス，インコーポレイテッド filed Critical エスジーエス―トムソン　マイクロエレクトロニクス，インコーポレイテッド
Publication of JPS60181055U publication Critical patent/JPS60181055U/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/817—Combinations of field-effect devices and resistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の応用例のメモリセルを使用しているＲ
ＡＭの一部のブロック回路図、第２図は第１図のメモリ
セルの電気回路図、第３図は第２図の回路の基板上の配
置図、第４図は第３図の■−■線における立話面図、第
５図は本考案に従って構成された負荷インピーダンス装
置を有するゲート相互接続部の好適実施例の断面図、第
６図は負荷インピーダンス装置の他の実施例によるゲー
ト相互接続部の断面図、第７Ａ図、第７Ｂ図、第８Ａ図
、第８Ｂ図、第９Ａ図、第９Ｂ図、第１０Ａ図、および
第１０Ｂ図は本考案に従って構成された負荷インピーダ
ンス装置の他の実施例の断面図である。 ２０・・・真性多結晶シリコン半導体層、２２・・・第
１導電路、２４．４３・・・第２導電路、２８・・・真
性−外回性接合。 ０Ｍ　　？／６ ０力Ｔ−一「夕１０ 〒〒 ｊ：ＦＩＧ、１ １１　　　　古”’　　　　Ｉｌ １　　　　　　　　　　　１ ＦＩＧ、２

Claims (1)

    【実用新案登録請求の範囲】
  1. 単結晶半導体材料の基板表面の部分上に絶縁層が被着さ
    れている前記基板上につくられた半導体インピーダンス
    構造において、前記絶縁層の一部の上に置かれ、第１の
    導電路を画定する実質的に真性の多結晶半導体材料の一
    体化基体と、該一体化基体の第１の領域内に置かれ、第
    ２導電路を画定する第１導電形の外因性不純物のドープ
    領域とをそなえ、前記外因性不純物ドープ領域と前記真
    性一体化基体との境界によって真性−外回性接合が画定
    され、前記第１導電路と前記第２導電路とが前記真性−
    外回性接合を通る電流に対する直列の電気的通路を画定
    することを特徴とする半導体インピーダンス構造。
JP1985060174U 1976-11-22 1985-04-22 半導体インピーダンス構造 Pending JPS60181055U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74381076A 1976-11-22 1976-11-22
US743810 1976-11-22

Publications (1)

Publication Number Publication Date
JPS60181055U true JPS60181055U (ja) 1985-12-02

Family

ID=24990283

Family Applications (6)

Application Number Title Priority Date Filing Date
JP13978177A Pending JPS5389382A (en) 1976-11-22 1977-11-21 Ic memory and method of producing same
JP57182678A Pending JPS5886763A (ja) 1976-11-22 1982-10-18 半導体インピ−ダンス構造とその製作方法
JP1985060174U Pending JPS60181055U (ja) 1976-11-22 1985-04-22 半導体インピーダンス構造
JP1985100415U Pending JPS6159360U (ja) 1976-11-22 1985-07-01
JP3200909A Expired - Lifetime JP2696110B2 (ja) 1976-11-22 1991-08-09 半導体インピーダンス装置
JP3200925A Expired - Lifetime JP2692439B2 (ja) 1976-11-22 1991-08-09 集積回路２進メモリセル

Family Applications Before (2)

Application Number Title Priority Date Filing Date
JP13978177A Pending JPS5389382A (en) 1976-11-22 1977-11-21 Ic memory and method of producing same
JP57182678A Pending JPS5886763A (ja) 1976-11-22 1982-10-18 半導体インピ−ダンス構造とその製作方法

Family Applications After (3)

Application Number Title Priority Date Filing Date
JP1985100415U Pending JPS6159360U (ja) 1976-11-22 1985-07-01
JP3200909A Expired - Lifetime JP2696110B2 (ja) 1976-11-22 1991-08-09 半導体インピーダンス装置
JP3200925A Expired - Lifetime JP2692439B2 (ja) 1976-11-22 1991-08-09 集積回路２進メモリセル

Country Status (5)

Country Link
JP (6) JPS5389382A (ja)
DE (1) DE2751481C2 (ja)
FR (2) FR2382744A1 (ja)
GB (2) GB1597725A (ja)
IT (1) IT1090938B (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453175A (en) * 1979-09-19 1984-06-05 Tokyo Shibaura Denki Kabushiki Kaisha MOS Static RAM layout with polysilicon resistors over FET gates
EP0032608A1 (en) * 1980-01-22 1981-07-29 Mostek Corporation Column line powered static ram cell
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
US4446613A (en) * 1981-10-19 1984-05-08 Intel Corporation Integrated circuit resistor and method of fabrication
JPS61134054A (ja) * 1984-12-04 1986-06-21 Nec Corp 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4922871A (ja) * 1972-06-20 1974-02-28
JPS5011644A (ja) * 1973-06-01 1975-02-06

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576478A (en) * 1969-07-22 1971-04-27 Philco Ford Corp Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode
GB1318856A (en) * 1971-03-18 1973-05-31 Ferranti Ltd Semiconductor devices
GB1391959A (en) * 1972-07-20 1975-04-23 Ferranti Ltd Semiconductor devices
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
CH581904A5 (ja) * 1974-08-29 1976-11-15 Centre Electron Horloger
DE2760086C2 (ja) * 1976-07-26 1988-02-18 Hitachi, Ltd., Tokio/Tokyo, Jp

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4922871A (ja) * 1972-06-20 1974-02-28
JPS5011644A (ja) * 1973-06-01 1975-02-06

Also Published As

Publication number Publication date
JPS5886763A (ja) 1983-05-24
JP2692439B2 (ja) 1997-12-17
JPH06188389A (ja) 1994-07-08
FR2382744B1 (ja) 1984-01-06
FR2382771B1 (ja) 1985-04-19
DE2751481C2 (de) 1986-10-23
GB1597725A (en) 1981-09-09
FR2382771A1 (fr) 1978-09-29
JP2696110B2 (ja) 1998-01-14
GB1597726A (en) 1981-09-09
IT1090938B (it) 1985-06-26
JPH0613577A (ja) 1994-01-21
FR2382744A1 (fr) 1978-09-29
JPS6159360U (ja) 1986-04-21
DE2751481A1 (de) 1978-06-08
JPS5389382A (en) 1978-08-05

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