JPS60187149A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the memory capacity by circulating information on the detection frequency state of a synchronizing pattern, etc. CONSTITUTION:When a signal with the synchronizing pattern is inputted to a shift register 5, five bits are supplied to a pattern detecting circuit 6 at the same time and a pattern detecting circuit 6 outputs logic ''1'' when a specific pattern appears. The contents of a shift register 8, on the other hand, are shifted with the same clock as the clock of input information and specific pattern detection frequency information is returned to a logical circuit part 7. The logical circuit part 7 when supplied with logic ''1'' from the pattern detecting circuit 6 while the value of pattern detection frequency information which is one frame before is (p) generates a value (p+1), which is written on the shift register 8 as 3-bit word information.

Description

DETAILED DESCRIPTION OF THE INVENTION (5) Technical Field of the Invention The present invention uses a frame synchronization circuit, in particular, monitors frame information having an m-bit synchronization pattern for a plurality of frames and detects a synchronization pattern.

9m in the frame synchronization circuit that establishes frame synchronization
The present invention relates to a frame synchronization circuit that reduces memory usage by storing the detected state of bit synchronization patterns in memory.

(C) Technical Background and Problems Traditionally, for example, as shown in Fig. 1, one frame consists of N bits, and a concentrated synchronization pattern 2 of m bits is added to the beginning of each frame, so to speak. is known to do. When establishing frame synchronization in such a communication system, considering that there is a possibility that the general information (=) may include a pattern that happens to match the above m-bit pattern, In other words, frame synchronization is established when A number of the above m-bit patterns 2 are detected consecutively.

Extract m bits each from the shift register 3' of NX(A-1)+m stages and the position substantially separated by N stages, and check whether each door pit has the same pattern as the concentrated opening pattern described above. The pattern detection circuit 4 detects the pattern. Then, frame synchronization is performed when all A (2) equivalent concentrated synchronization patterns are detected.

In the case of the conventional configuration shown in FIG. 29, for example, N=10'0゜m,
= 5 and A = 7, a memory with a capacity of 605 bits i.delta.: is required as the shift register 3.

0 Object and Structure of the Invention The present invention aims to reduce the capacity of the memory, and provides a frame synchronization system that reduces the capacity by circulating information such as the number of times the synchronization pattern has been detected. The purpose is to provide circuits.

And for that.

The frame synchronization circuit of the present invention receives a signal sequence having a synchronization pattern of m bits in N bits.1. ,, in a digital communication system that performs frame synchronization by detecting the m-bit synchronization pattern that should appear in an N-bit period, an m-bit pattern detection circuit that detects the m-bit synchronization pattern; One word Log that records the above frame synchronization protection information for each phase.
, Δ or more]-, and the frame synchronization protection information of one cycle before read from the memory and the detection output from the m-bit pattern detection circuit. The present invention is characterized in that it has a logic circuit section that generates frame synchronization protection information to be newly written to the memory and writes it into the memory, and performs the frame synchronization protection processing for all phases. . This will be explained below with reference to the drawings.

(2) Embodiment of the Invention FIG. 3 shows the configuration of an embodiment of the present invention, and FIG. 4 shows a transition diagram illustrating the operation of the logic circuit section shown in the configuration of the embodiment of the invention.

In FIG. 3, 5 is a 1-bit m-stage shift register;
Reference numeral 6 denotes an m-bit concentrated synchronization pattern detection circuit, which corresponds to the case where the pattern is given as "10100" from the beginning in the illustrated case, and 7 denotes a logic circuit section, which is shown in FIG. 8 represents a 3-bit x 100-stage shift register constituted by a memory, I7, which generates pattern detection frequency information corresponding to the transition diagram. In addition, in the case of 9 illustrations, N=10
0°A=7. It corresponds to m=5.

When the information as shown in FIG. 1 is transmitted bit by bit, five bits on the shift register 5 are simultaneously supplied to the pattern detection circuit 6.

The pattern detection circuit 6 outputs logic "1" when two consecutive patterns "10100j" appear. That is, the pattern detection circuit 6 performs 1. It may be considered to monitor whether the pattern r10100J exists.

The shift register 8 is shifted by the same clock as the clock of the input information, and the pattern detection number information stored at the position corresponding to the phase position exactly N bits before is transferred to the logic circuit section 7. It has been returned. In the logic circuit section 7, as shown in the illustrated transition diagram of FIG. 4, when the value of the pattern detection number information indicated by - for one frame before is p.

When a logic "1" is applied from the pattern detection circuit 6 to 1+, a value (F+1) is generated and acquired in the shift register 8 as 3-bit 1-word information. Also, the value of the pattern detection number information one frame before was p, but the pattern detection circuit 6 sent the logic L! I! If r-r'n is given, the value "0" is generated and the shift register 8 is filled with l'-
Written as 000J. In the case shown in FIG. 4, if pattern detection continues after the pattern detection number information reaches IIIJ, it remains at ll 1 ], , 1. Needless to say, the pattern detection number information is
11. If I J, there are 7 synchronization patterns (A
'=7) means detected and frame synchronization is established.

In the case of the configuration shown in FIG. 3, what is the capacity required for the shift ◆ register 8?

The number of bits is N x (logx A ) bits, and the shift register 5 requires bits, so N=lOO, m bits are sufficient.

■ Circulating the information on the effect layer of the invention is especially advantageous when the above-mentioned mercenary is large.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining information with a concentrated synchronization pattern, FIG. 2 is an example of a conventional frame synchronization circuit, FIG. 3 is a configuration of an embodiment of the present invention, and FIG. 4 is an embodiment of the present invention. A transition diagram illustrating the operation of the logic circuit section shown in the configuration is shown. In the figure, 1 is a frame and 2 is a concentrated synchronization pattern. Reference numeral 6 represents an m-bit concentrated synchronization pattern detection circuit, 7 represents a logic circuit section, and 8 represents a memory that performs an operation corresponding to a shift register.

Claims (1)

[Claims] A signal sequence with an m-bit synchronization pattern in N bits was received, and the m-bit synchronization pattern that should appear every N bits was detected (-Therefore, in a digital communication system that performs frame synchronization, the m-bit synchronization pattern is detected) an m-bit pattern detection circuit that detects a pattern;
A memory constituting an N-stage shift register having 8 or more bits stores the protection information for frame synchronization in each f1'L phase 1σ of the bit period, and and a logic circuit section that generates frame synchronization protection information to be newly written in the memory based on the frame synchronization protection information and the detection output from the m-bit pattern detection circuit, and writes the generated frame synchronization protection information in the memory. , A frame synchronization circuit characterized in that the frame synchronization protection processing described above is applied to all phases.