JPS60251671A - Field-effect type transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce contact resistance, and to improve reliability by a method wherein a metallic layer is formed onto a channel semiconductor layer, a source electrode and a drain electrode are shaped and a recess as a channel layer is formed, an insulating film is shaped onto the side wall of the recess and a gate electrode is formed onto the base. CONSTITUTION:An n type GaAs channel layer 22 and an n<+> type GaAs contact layer 23 are grown continuously onto a semi-insulating GaAs substrate 21 in an epitaxial manner, and an Au/AuGe source electrode 24 and an Au (an upper layer)/AuGe (a lower layer) drain electrode 25 are further formed onto the n<+> type contact layer. The source electrode 24 and the drain electrode 25 are patterned while being self-aligned with these layers 22 and 23, and a recess reaching to the n type channel layer 22 is shaped while penetrating the n<+> type contact layer 23. The side wall of the recess is assisted by an Si3N4 insulating film 26, and an Al gate electrode 27 is formed on the bottom of the recess in the width of the recess. Accordingly, currents between a source and a drain can be monitored on the formation of the gate electrode, resistance between the source and the drain is reduced, and drain withstanding voltage can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a field effect transistor (PET) and a method for manufacturing the same, particularly a recessed sidewall assisted self-line type FET.
It relates to ET and its manufacturing method.

Technical Background In order to obtain high-speed, high-gain FETs, element dimensions are being miniaturized, and cell alignment technology that uses high-resolution phosphorography such as electron beam exposure, ion implantation, dry etching, etc. is being actively developed.

F with an insulating film of sz, N4, etc. sandwiched between the contact electrodes (source, drain electrodes) of etc. and the gate electrode of kt etc.
ET structure has been devised (IEICE Technical Report 8SD83-11
2), Figure 7 shows an example of its structure, where 1 is a GgAs substrate, 2 is an n-type GaAs channel layer, and 3 is an At gate layer.
electrode, 4 is Au/AuQ6 source electrode%5 is Au/Au
Ge drain electrode, 6 is 5t3N4 insulating film.

The thickness of the n-type GaAs layer 2 is about Q, spm, whereas the thickness of the Si3N4 film 6 is only about several hundred nm, so the resistance between the source and gate and between the gate and drain is Can be made very small. In FETs, generally, reducing the resistance between the source and gate and between the gate and drain contributes to increasing high frequency characteristics and amplification factor. However, in the above Selfa line structure, the contact electrode 4
．． Since the gate electrode 3 is formed before the gate electrode 5, the source/drain current cannot be checked before forming the gate electrode. Furthermore, the drain electrode 5, the insulating film 6 and the n-type Ga
Since the electric field is concentrated at the contact point of the As layer, there is a problem that the withstand voltage is not high.

On the other hand, a technique is known in which a recess is formed in the channel layer and a gate electrode is formed within the recess.

FIG. 8 is an example. In the figure, 11 is GaAs
Substrate %12 is n-type GaAs s channel layer, 13 is n+
type GaAs contact layer, 14 is an At gate electrode, 15
16 is an Au/AuGe source electrode, 16 is an Au/AuGe drain electrode, and 17 is a Si3N4 insulating film. In this structure, the source of the n-type GaAs channel layer 12
Since the thickness between the gates and between the gate and drain is large, the resistance between the source and gate and between the gate and drain can be reduced, and the pinch-off voltage can also be high. Moreover, since the recess can be formed by monitoring the source-drain current, the source-drain current can be adjusted. In addition, the source electrode 15 and the drain electrode 16 and the n-type Ga A
n+ GaAs contact layer 15 between s channel layer 12
can be inserted. Furthermore, the electric field applied between the source and drain is applied to the n+GaAs contact layer 13, the n-type GaAs channel layer 12, and the Si, N4 insulating film 1.
7 common contacts, as well as distributed at the corners of the recess, so
The pressure resistance will be much higher. However, this structure is not a self-line structure.

Purpose of the Invention An object of the present invention is to be able to monitor the current between the source and drain before forming the gate electrode, and to introduce a highly concentrated contact layer under the source and drain electrodes in order to reduce contact resistance and improve reliability. It is an object of the present invention to provide a recess sidewall assisted self-line FET structure with a short gate length and short electrode spacing, which can be made into a recessed structure for high breakdown voltage and high pinch-off voltage.

Structure of the Invention In order to achieve the above object, in the present invention, a metal layer for a source ψ drain electrode (optionally a high concentration contact layer and) is formed on a channel semiconductor layer, and a source electrode and a drain electrode are formed. A recess is formed in the channel layer using self-alignment. Then, an insulating film is formed on the side walls of this recess, and a gate electrode is formed on the bottom surface of the recess.

Thus, the present invention provides a recessed sidewall assisted self-line FET and a method for manufacturing the same. The details will be explained in the following examples with reference to the drawings.

Embodiment of the Invention FIG. 1 shows a recess sidewall assist cell 7 align F] 13T according to an embodiment of the invention. An n-type GaAs channel layer 22 and an n+-type GaAs are formed on a semi-insulating GaAs substrate 21.
The s-contact layer 23 is continuously connected to the epitaxial drain electrode 25.
is formed. Then, at the same time as the source electrode 24 and drain electrode 25 are patterned, a recess is formed that is self-aligned with these, penetrates the n+ type contact layer 26, and reaches the n type channel layer 22. The side walls of this recess are assisted by an sr3N4 insulating film 26, and an At gate electrode 27 is formed at the bottom of the recess to the width of the recess.

The FID T can drive current between the source and drain when forming the gate electrode, and since the gate electrode portion has a recessed structure, the resistance between the source and drain can be reduced and the drain breakdown voltage can be increased. Moreover, by introducing an n+GaAs contact layer, it is possible to achieve low resistance and high reliability, and since the source and drain electrodes and gate electrode have a self-line structure, there is no need for highly accurate mask alignment. Armor-type interpolar structures can be formed with good reproducibility.

The manufacturing of EFT will be described below.

In FIG. 2, n-type GaAs, Q (S concentration of about 10" cm-3) is deposited on a semi-insulating GaAs substrate 21.
22 to a thickness of 0.5 to 0.4 pm,
The As layer (S concentration about 1018i3) 23 has a thickness of 0.1
Continuous epitaxial growth to ~0.2 μm. On top of that is an Au/AuGe layer (Au layer 600-350 nm thick).

An AuGe layer (20 to 30 nm) 25 is formed by vapor deposition, and a Si3N4 layer 31 is further deposited to a thickness of 300 to 350 nm by CVD.
Form about m. Then, a resist layer 32 is applied,
Pattern into a recess shape.

Since the gate length is approximately 0.2 to 2 μm, the dimensions for patterning the resist are determined in consideration of the thickness of the Si and N4 films 26 on the side walls of the recess.

In FIG. 3, using the patterned resist layer 32 as a mask, ion beam etching f7'' is carried out, and Au/Au
The Ge layer 25, the n-type GaAs drop 25 are passed through the page, and the n-type (
) forming a recess that reaches the aAs layer 22; after that,
When a s r 5N4 film is deposited by plasma CVD method,
Si and N4 adhere not only to the base Si3N4 film 31 but also to the inner surface of the recess. The thickness of the 513N4 film 26 on the recess surface is approximately 30 nm.

In Figure 4, when anisotropic ion beam etching is performed, the film thickness at the bottom of the recess is thin;
is N 4 26 can be selectively removed. Then, the remaining 5i5N4 film 26,! N-type GaAs layer 2 at the bottom of the recess opened using 11 as a mask
Wet etching 2.

This chemical etching is performed to remove the surface of the n-type GaAs layer 22 damaged by the ion beam etching, and at the same time, by monitoring the source-drain current, the bottom of the recess of the n-type GaAs layer 22 is etched. This is done to control the film thickness and adjust the source-drain current.

In FIG. 5, after the adjustment of the source-drain current is completed, an aluminum layer 27 is applied to the entire surface to a thickness of 400 to 500 nm.
Deposit about m. When a resist film 33 is applied thereon, the surface of the resist film 35 is flattened. Then, when ion beam etching was performed, there was no big difference in the etching speed between the resist and aluminum 27, so the resist in the recess was left and the remaining resist and 5i5N4 were etched.
The aluminum on film 61 is removed (see FIG. 6).

After that, the resist in the recess is removed and the 8i
A window is opened in the 3N4 film 31 and the TIA u wiring layer 28 (
1), the recess sidewall assisted self-line FET according to the present invention is completed.

It should be understood that the above description is merely an example, and that the present invention can be freely modified within the scope of the claims.

Effects of the Invention According to the present invention, the gate electrode can be formed by monitoring the source-drain current, and a high concentration layer for contact compensation can be introduced under the source electrode and the drain electrode.
A recess sidewall assisted self-line FET is provided which has a high breakdown voltage due to its recessed structure, and has a short gate length and short electrode spacing due to the self-aligned self-line.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an FET according to an embodiment of the present invention, and FIG.
Fig. 6 is a cross-sectional view of the FET in the process of manufacturing the FET shown in Fig. 1, Fig. 7 is a cross-sectional view of a conventional example of a short electrode spacing FET to which the self-line technology is applied, and Fig. 8 is a cross-sectional view of a conventional example of a recessed structure FE. 'T is a sectional view. 21...Substrate, 22...n-type GaAs layer (channel layer), 23...n+decade aAs layer (contact layer), 25...A u /A u G e layer (source/drain electrode) ), 26...Si3N4 film, 27.
...At layer (gate electrode), 28-TiAu layer.・Figure 1 Figure 2 Figure 3 Figure 6 Figure 4 6 7 Figure 6

Claims (1)

[Claims] 1. A source electrode and a drain electrode are provided on a semiconductor layer forming a channel layer, and a recess is formed in the semiconductor layer in alignment with opposing side surfaces of the source electrode and the drain electrode, an insulating film is provided on the surface of a vertical wall formed by the side walls of the electrode and the drain electrode and the side walls of the recess in the semiconductor layer, and the semiconductor layer and the insulating film are provided in the recess in the semiconductor layer. A field effect transistor characterized by having a gate electrode in contact with. 2. A step of forming a first metal layer on a substrate having a conductive semiconductor layer on its surface, and a step of forming a recess that penetrates the first metal layer and reaches a predetermined depth within the semiconductor layer. an electric field characterized by comprising the steps of: selectively forming an insulating film on the side walls of the recess; and selectively forming a second metal layer on the semiconductor layer exposed within the recess. A method of manufacturing an effect type transistor. 5. The method according to claim 2, wherein another semiconductor layer doped with impurities at a high concentration is interposed between the semiconductor layer and the first metal layer.