JPS60257549A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60257549A JPS60257549A JP59115896A JP11589684A JPS60257549A JP S60257549 A JPS60257549 A JP S60257549A JP 59115896 A JP59115896 A JP 59115896A JP 11589684 A JP11589684 A JP 11589684A JP S60257549 A JPS60257549 A JP S60257549A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- external connecting
- external connection
- semiconductor device
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/306—Assembling printed circuits with electric components, e.g. with resistors with lead-in-hole components
- H05K3/308—Adaptations of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は例えば小、中電力サイリスク等の半導体製品に
実施して好適な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device suitable for implementation in semiconductor products such as small- and medium-power silicones.
従来、この種の半導体装置は第1図に示すように構成さ
れており、これを同図に基づいて説明すると、1は厚片
で形成された放熱板、2,3および4は矩形状の薄片か
らなりその表面が半田により被覆される外部接続リード
、5はこれらリード2.3および4に接続する半導体素
子(図示せず)を樹脂封止するモールド部である。なお
、放熱板1および外部接続リード2,3.4の素材とし
ては通常銅合金が用いられており、その表面にはニッケ
ル等の金属が2〜5μの厚さでメンキされている。また
、半導体装置は通常製造ラインの自動化のため複数個連
続して製造され、半導体素子を樹脂封止した後にそれぞ
れ切り離される。Conventionally, this type of semiconductor device has been constructed as shown in FIG. External connection leads 5 are made of thin pieces and the surfaces thereof are covered with solder. Reference numeral 5 designates a mold portion for resin-sealing semiconductor elements (not shown) connected to these leads 2, 3 and 4. Note that copper alloy is usually used as the material for the heat sink 1 and the external connection leads 2, 3.4, and the surface thereof is coated with a metal such as nickel to a thickness of 2 to 5 microns. Furthermore, semiconductor devices are usually manufactured in series in a plurality to automate the manufacturing line, and are separated from each other after the semiconductor elements are sealed with resin.
このように構成された半導体装置を顧客が基板に実装す
る場合、外部接続リード2,3および4の半田付作業を
容易にできるように、前記メッキ被膜した外部接続リー
ド表面に半田コーティング処理が施される。When a customer mounts a semiconductor device configured in this manner on a board, a solder coating process is applied to the plated surface of the external connection leads to facilitate soldering of the external connection leads 2, 3, and 4. be done.
この半田コーティング方法には、半田メンキ。This solder coating method requires solder coating.
半田浸漬等による方法があるが、一般にはその作業性お
よび信頼性を考慮して半田浸漬法が採用されている。Although there are methods such as solder dipping, the solder dipping method is generally adopted in consideration of its workability and reliability.
この半田浸漬法を用いると、第2図に示すように、外部
接続リード2.3および4を半田6が溶融する浴槽7内
に半田コーティング所望部分まで浸漬した後、半導体装
置を上方に引き上げることにより外部接続リード2,3
および4の半田コーティングを行うことができる。この
場合半田コーティングが容易に行えるように前処理とし
て、外部接続リード2,3および4を希塩酸等に数秒間
浸漬して、リード表面に施したニッケル被膜表面上の酸
化物を除去し、ニッケル被膜表面を清浄にしておく必要
がある。また、浴槽7内の半田6は通常□鉛−錫の共晶
半田が用いられ280℃の温度にコントロールされてい
る。When this solder immersion method is used, as shown in FIG. 2, after the external connection leads 2, 3 and 4 are immersed in a bath 7 in which the solder 6 is melted to the desired part to be coated with solder, the semiconductor device is pulled upward. External connection leads 2 and 3
and 4 solder coating can be performed. In this case, as a pretreatment to facilitate solder coating, the external connection leads 2, 3, and 4 are immersed in dilute hydrochloric acid for a few seconds to remove the oxide on the surface of the nickel coating applied to the lead surface, and remove the nickel coating. The surface must be kept clean. Further, the solder 6 in the bathtub 7 is normally □lead-tin eutectic solder, and the temperature is controlled at 280°C.
このようにして行われる半田浸漬法においては、外部接
続リード2,3および4が浴槽7内にある半導体装置の
引き上げ時にリードの先端方向に半凝固状態の半田が流
れ、第3図に示すようにモールド部5の近傍の部分に比
較して先端部分の半田コーティング被膜8が厚くなる。In the solder dipping method carried out in this manner, when the semiconductor device with the external connection leads 2, 3, and 4 is pulled up from the bath 7, semi-solidified solder flows toward the tips of the leads, as shown in FIG. The solder coating film 8 at the tip portion is thicker than the portion near the mold portion 5.
したがって、従来の半導体装置を基板(図示せず)に実
装する場合、外部接続リード2,3および4を基板に設
けた孔(図示せず)に挿入することが困難になり、この
挿入作業を自動化する場合J’ には尚更支障があった
。Therefore, when mounting a conventional semiconductor device on a board (not shown), it is difficult to insert the external connection leads 2, 3, and 4 into holes (not shown) provided in the board, and this insertion work is difficult. J' was even more problematic when automated.
1′1
J すなわち、前記基板の孔径は基板の高密度性を保つ
ためにその大きさが限定されており、また孔ピッチは外
部接続リード2,3および4のピッチに対応するように
設計されているからである。1'1 J In other words, the hole diameter of the board is limited in order to maintain the high density of the board, and the hole pitch is designed to correspond to the pitch of the external connection leads 2, 3, and 4. This is because
本発明はこのような事情に鑑みなされたもので、その表
面が半田により被覆される外部接続リードの両側縁に幅
方向に開口する凹部を設けるというきわめて簡単な構成
により、外部接続リードの半田コーティングが良好に行
える半導体装置を提供するものである。以下、その構成
等を図に示す実施例によって詳細に説明する。The present invention has been developed in view of the above circumstances, and has an extremely simple configuration in which recesses opening in the width direction are provided on both sides of the external connection lead whose surface is coated with solder. The present invention provides a semiconductor device that can perform satisfactorily. Hereinafter, the configuration and the like will be explained in detail with reference to embodiments shown in the drawings.
第4図は本発明に係る半導体装置を示す断面図で、第1
図乃至第3図と同一の部材については同一の符号を付し
、詳細な説明は省略する。同図において、符号11で示
すものは幅方向に開口する凹部で、前記外部接続リード
2.3および4の両側縁に各−個設けられており、それ
ぞれが互いにリード長手方向に異なる位置に位置付けら
れている。これら凹部11の切込み深さは、リード材料
り曲げ強度を考慮してリード幅の1ノ5以下に抑えられ
ており、半田コーティング時に凹部内に溶融半田が導入
される。FIG. 4 is a cross-sectional view showing a semiconductor device according to the present invention, and FIG.
Components that are the same as those in FIGS. 3 to 3 are designated by the same reference numerals, and detailed explanations will be omitted. In the same figure, what is indicated by the reference numeral 11 is a recessed portion opening in the width direction, which is provided on both side edges of the external connection leads 2.3 and 4, and each is positioned at a different position in the longitudinal direction of the lead. It is being The depth of cut of these recesses 11 is suppressed to 1/5 or less of the lead width in consideration of the bending strength of the lead material, and molten solder is introduced into the recesses during solder coating.
このように構成された半導体装置においては、外部接続
リード2,3および4が浴槽7内にある半導体装置の引
き上げ時に、外部接続リードの先端方向に流れる半凝固
状態の半田が凹部11内に導入されるため、従来のよう
にモールド部5の近傍の部分に比較して先端部分の方が
半田コーティング被膜8が厚くなることがなくなり、外
部接続リード2.3および4の表面には略等しい厚さの
半田コーティング被膜8が形成される。In the semiconductor device configured in this manner, when the semiconductor device with the external connection leads 2, 3, and 4 is pulled up from the bathtub 7, semi-solidified solder flowing toward the tips of the external connection leads is introduced into the recess 11. Therefore, the solder coating film 8 does not become thicker at the tip end than in the vicinity of the mold part 5 as in the past, and the surfaces of the external connection leads 2.3 and 4 have approximately the same thickness. A third solder coating film 8 is formed.
なお、本実施例においては、凹部11が外部接続リード
2,3および4の両側縁に各−個設ける例を示したが、
本発明はこれに限定されず、凹部11内に流れ込む半田
量によって複数個設けても勿論よい。In this embodiment, an example is shown in which the recesses 11 are provided on both side edges of the external connection leads 2, 3, and 4, respectively.
The present invention is not limited to this, and it goes without saying that a plurality of them may be provided depending on the amount of solder flowing into the recess 11.
以上説明したように本発明によれば、その表面が半田に
より被覆される外部接続リードの両側縁に幅方向に開口
する凹部を設けたので、外部接続リードが半田浴槽内に
ある半導体装置の引き上げ時に、外部接続リードの先端
方向に流れる半凝固状態の半田が凹部内に導入されるこ
とになり、外部接続リードの半田コーティングを良好に
行うことができる。したがって、半導体装置を基板に実
装するに際し、基板に設けた孔に対する外部接続リード
の挿入作業を容易に行うことができる。As explained above, according to the present invention, recesses opening in the width direction are provided on both sides of the external connection leads whose surfaces are covered with solder, so that a semiconductor device whose external connection leads are in a solder bath can be lifted up. At times, semi-solidified solder flowing toward the tip of the external connection lead is introduced into the recess, and the external connection lead can be well coated with solder. Therefore, when mounting a semiconductor device on a substrate, it is possible to easily insert external connection leads into holes provided in the substrate.
第1図は従来の半導体装置を示す断面図、第2図は半導
体装置の外部接続リードの半田コーティング実施状態を
示す断面図、第3図は外部接続リードを半田コーティン
グした半導体装置を示す断面図、第4図は本発明に係る
半導体装置を示す断面図である。
2、 3. 4・・・・外部接続リード、11・・・・
凹部。
代理人 大岩増雄FIG. 1 is a cross-sectional view showing a conventional semiconductor device, FIG. 2 is a cross-sectional view showing how the external connection leads of the semiconductor device are coated with solder, and FIG. 3 is a cross-sectional view showing the semiconductor device with the external connection leads coated with solder. , FIG. 4 is a sectional view showing a semiconductor device according to the present invention. 2, 3. 4... External connection lead, 11...
recess. Agent Masuo Oiwa
Claims (1)
外部接続リードを備えた半導体装置において、前記外部
接続リードの両側縁に幅方向に開口する凹部を設けたこ
とを特徴とする半導体装置。1. A semiconductor device comprising an external connection lead connected to a semiconductor element and whose surface is covered with solder, characterized in that a recess opening in the width direction is provided on both side edges of the external connection lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59115896A JPS60257549A (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59115896A JPS60257549A (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60257549A true JPS60257549A (en) | 1985-12-19 |
Family
ID=14673877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59115896A Pending JPS60257549A (en) | 1984-06-04 | 1984-06-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60257549A (en) |
-
1984
- 1984-06-04 JP JP59115896A patent/JPS60257549A/en active Pending
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